C. Selvanayagam | Amd - Academia.edu (original) (raw)

Papers by C. Selvanayagam

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technolo... more The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-µm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of Manuscript the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011

With the most popular electronic products being the slimmest ones with the highest functionality,... more With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3-D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5 × 10 −6 /°C) and silicon (2.5 × 10 −6 /°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this paper, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for: 1) designing substrates with TSVs such that mobility in the active devices are not affected by the presence of TSVs, and 2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011

Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when pla... more Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints, comprised of completely of IMC compounds, will fail in a sudden unexpected manner as compared to normal solder joints, which fail in a ductile manner, where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress, during post-formation cooling down to room temperature, increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that, with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also been performed in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance than the samples with the conventional full pad design.

2009 11th Electronics Packaging Technology Conference, 2009

ABSTRACT With the most popular electronics products being the slimmest ones with the highest func... more ABSTRACT With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5×10-6/°C) and silicon (2.5×10-6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this study, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for (1) designing substrate with TSVs such that mobility in the active devices are not affected by the presence of TSVs and (2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008

This paper presents a study of the resistance of solder joints to failure when subjected to strai... more This paper presents a study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop impact on a portable electronic product. Two test methods are used in this study: board-level drop/shock test (BLDT) and component-level ball impact test (BIT). The performance of 12 material combinations consisting of 6 solder alloys and 2 pad finishes were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristics, namely, number of drops to failure for BLDT and peak load, total fracture energy, and energy to peak load for BIT, were evaluated. Analysis of the test results indicates that there is a lack of universal correlation between BLDT and BIT. Nevertheless, BIT can still serve as a test methodology for quality assurance in view of the strong correlation between the measured BIT characteristics and the failure mode. The total fracture energy parameter is preferred over the peak load and energy to peak load due to its higher sensitivity and reduced susceptibility to measurement error.

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012

ABSTRACT


Medium strain rate (0.1/s to 300/s) constitutive properties are needed for accurate modeling of d... more Medium strain rate (0.1/s to 300/s) constitutive properties are needed for accurate modeling of drop impact conditions. This study presents an experimental procedure for obtaining the material properties of solder alloys at these medium strain rates. The effect of grain size on the medium strain rate behavior of solder alloys is also studied, using SnPb alloy as an example. Grain

Microelectronics Reliability, 2008

This paper presents a comprehensive study of the resistance of solder joints to failure when subj... more This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop-impact on a portable electronic product. Two test methods are used in this study: the board level drop/shock test (BLDT) and the component level ball impact shear test (BIST). The performance of (i) 12 material combinations consisting of six solder alloys and two pad finishes; and (ii) 11 manufacturing variations covering three vendors, two finishes, three immersion gold thicknesses and three thermal aged conditions, were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristic parameters -number of drops to failure for BLDT and peak load, total fracture energy, and energy-to-peak load for BIST -were evaluated. The lack of universal correlations between the two test methods has ruled out the use of BIST for evaluating solder joint materials, but BIST is recommended as a test method for quality assurance in view of the strong correlation between the measured parameters and the failure mode. The total fracture energy parameter is preferred over the peak load and energy-to-peak load due to its higher sensitivity and reduced susceptibility to measurement error.

Journal of Electronic Materials, 2008

The stress-strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 ... more The stress-strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 s -1 and 300 s -1 are required to support finite-element modeling of the solder joints during board-level mechanical shock and productlevel drop-impact testing. However, there is very limited data in this range because this is beyond the limit of conventional mechanical testing and below the limit of the split Hopkinson pressure bar test method. In this paper, a specialized drop-weight test was developed and, together with a conventional mechanical tester, the true stress-strain properties of four solder alloys (63Sn-37Pb, Sn-1.0Ag-0.1Cu, Sn-3.5Ag, and Sn-3.0Ag-0.5Cu) were generated for strain rates in the range from 0.005 s -1 to 300 s -1 . The sensitivity of the solders was found to be independent of strain level but to increase with increased strain rate. The Sn-3.5Ag and the Sn-3.0Ag-0.5Cu solders exhibited not only higher flow stress at relatively low strain rate but, compared to Sn-37Pb, both also exhibited higher rate sensitivity that contributes to the weakness of these two lead-free solder joints when subjected to drop impact loading.

IEEE Transactions on Electronics Packaging Manufacturing, 2000

The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impac... more The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimize the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines crack-front mapping using the dye and pry method and electrical FE simulation to establish a

IEEE Transactions on Advanced Packaging, 2000

Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The ... more Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10 -6 / o C) is a few times higher than that of silicon (~2.5x10 -6 / o C). Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO 2 ), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10x10 -6 / o C. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps.

2009 59th Electronic Components and Technology Conference, 2009

Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin... more Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21x21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 μm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25x25x0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45x45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technolo... more The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-µm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of Manuscript the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011

With the most popular electronic products being the slimmest ones with the highest functionality,... more With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3-D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5 × 10 −6 /°C) and silicon (2.5 × 10 −6 /°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this paper, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for: 1) designing substrates with TSVs such that mobility in the active devices are not affected by the presence of TSVs, and 2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2011

Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when pla... more Low-temperature bonds are thin intermetallic (IMC) bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints, comprised of completely of IMC compounds, will fail in a sudden unexpected manner as compared to normal solder joints, which fail in a ductile manner, where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress, during post-formation cooling down to room temperature, increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that, with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also been performed in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance than the samples with the conventional full pad design.

2009 11th Electronics Packaging Technology Conference, 2009

ABSTRACT With the most popular electronics products being the slimmest ones with the highest func... more ABSTRACT With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5×10-6/°C) and silicon (2.5×10-6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this study, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for (1) designing substrate with TSVs such that mobility in the active devices are not affected by the presence of TSVs and (2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

2008 3rd International Microsystems, Packaging, Assembly & Circuits Technology Conference, 2008

This paper presents a study of the resistance of solder joints to failure when subjected to strai... more This paper presents a study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop impact on a portable electronic product. Two test methods are used in this study: board-level drop/shock test (BLDT) and component-level ball impact test (BIT). The performance of 12 material combinations consisting of 6 solder alloys and 2 pad finishes were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristics, namely, number of drops to failure for BLDT and peak load, total fracture energy, and energy to peak load for BIT, were evaluated. Analysis of the test results indicates that there is a lack of universal correlation between BLDT and BIT. Nevertheless, BIT can still serve as a test methodology for quality assurance in view of the strong correlation between the measured BIT characteristics and the failure mode. The total fracture energy parameter is preferred over the peak load and energy to peak load due to its higher sensitivity and reduced susceptibility to measurement error.

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC), 2012

ABSTRACT


Medium strain rate (0.1/s to 300/s) constitutive properties are needed for accurate modeling of d... more Medium strain rate (0.1/s to 300/s) constitutive properties are needed for accurate modeling of drop impact conditions. This study presents an experimental procedure for obtaining the material properties of solder alloys at these medium strain rates. The effect of grain size on the medium strain rate behavior of solder alloys is also studied, using SnPb alloy as an example. Grain

Microelectronics Reliability, 2008

This paper presents a comprehensive study of the resistance of solder joints to failure when subj... more This paper presents a comprehensive study of the resistance of solder joints to failure when subjected to strain rates that simulate the conditions of drop-impact on a portable electronic product. Two test methods are used in this study: the board level drop/shock test (BLDT) and the component level ball impact shear test (BIST). The performance of (i) 12 material combinations consisting of six solder alloys and two pad finishes; and (ii) 11 manufacturing variations covering three vendors, two finishes, three immersion gold thicknesses and three thermal aged conditions, were investigated using these two test methods, and analysis of correlations between the methods was performed. Quantitative correlation and sensitivity coefficients for the failure modes and the measured characteristic parameters -number of drops to failure for BLDT and peak load, total fracture energy, and energy-to-peak load for BIST -were evaluated. The lack of universal correlations between the two test methods has ruled out the use of BIST for evaluating solder joint materials, but BIST is recommended as a test method for quality assurance in view of the strong correlation between the measured parameters and the failure mode. The total fracture energy parameter is preferred over the peak load and energy-to-peak load due to its higher sensitivity and reduced susceptibility to measurement error.

Journal of Electronic Materials, 2008

The stress-strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 ... more The stress-strain properties of eutectic Sn-Pb and lead-free solders at strain rates between 0.1 s -1 and 300 s -1 are required to support finite-element modeling of the solder joints during board-level mechanical shock and productlevel drop-impact testing. However, there is very limited data in this range because this is beyond the limit of conventional mechanical testing and below the limit of the split Hopkinson pressure bar test method. In this paper, a specialized drop-weight test was developed and, together with a conventional mechanical tester, the true stress-strain properties of four solder alloys (63Sn-37Pb, Sn-1.0Ag-0.1Cu, Sn-3.5Ag, and Sn-3.0Ag-0.5Cu) were generated for strain rates in the range from 0.005 s -1 to 300 s -1 . The sensitivity of the solders was found to be independent of strain level but to increase with increased strain rate. The Sn-3.5Ag and the Sn-3.0Ag-0.5Cu solders exhibited not only higher flow stress at relatively low strain rate but, compared to Sn-37Pb, both also exhibited higher rate sensitivity that contributes to the weakness of these two lead-free solder joints when subjected to drop impact loading.

IEEE Transactions on Electronics Packaging Manufacturing, 2000

The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impac... more The higher stiffness of Pb-free SAC solders makes Pb-free assemblies more sensitive to drop impact. In order to be able to optimize the drop test performance, it is necessary to have better insight into the crack propagation in the Pb-free solder joints. This study combines crack-front mapping using the dye and pry method and electrical FE simulation to establish a

IEEE Transactions on Advanced Packaging, 2000

Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The ... more Most of TSVs are filled with the copper, even siliconpoly and tungsten are the alternatives. The coefficient of thermal expansion (CTE) of copper (~17.5x10 -6 / o C) is a few times higher than that of silicon (~2.5x10 -6 / o C). Thus, when the copper filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the copper and the silicon/dielectric (e.g., SiO 2 ), which will create very large stresses and strains at the interfaces between the copper and the silicon and between the copper and the dielectric. These stresses/strains can be high enough to introduce delamination between the interfaces. In this study, the nonlinear thermal stresses and strains at the interfaces between the copper, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the silicon thickness and the TSV diameter). One of the major applications of TSV is as an interposer. Because of Moore's (scaling/integration) law, the silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional substrates, e.g., BT (bismaleimide triazine) cannot support these kinds of silicon chips anymore and a silicon interposer (substrate) is needed to redistribute the very fine-pitch and high pin-count pads on the chip to much larger pitch and less pin-count through the silicon vias on the silicon substrate. Depending on the via-size and pitch of the copper filled TSV, the effective CTE of the copper filled TSV interposer could be as high as 10x10 -6 / o C. Consequently, the global thermal expansion mismatch between the silicon chip and the copper filled TSV substrate can be very large and the bumps (usually very small, e.g., microbumps) between them may not be able to survive under thermal conditions. In this study, the nonlinear stresses and strains in the microbumps between the silicon chip and copper filled TSV interposer (with and without underfills) have been determined for a wide-range of via sizes and pitches, and various temperature conditions. These results should be useful for (1) making a decision if underfills are necessary for the reliability of microbumps, and (2) selecting underfill materials to minimize the stresses and strains in the microbumps.

2009 59th Electronic Components and Technology Conference, 2009

Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin... more Because of Moore's (scaling/integration) law, the Cu/lowk silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21x21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 μm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25x25x0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45x45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.