Bharathababu Kannan | Anna University (original) (raw)

Uploads

Papers by Bharathababu Kannan

Research paper thumbnail of Implementation of Vedic Multiplier For Digital Signal Processing

… conference on VLSI …, Jan 1, 2011

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast mult... more Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms, etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. Urdhava tiryakbhyam is the general multiplication formula applicable to all cases of multiplication. The coding is done in VHDL (very high speed integrated circuit hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after the synthesis is compared with normal multiplier. Further, this Vedic multiplier is used in matrix multiplication. This Vedic multiplier can bring great improvement in the DSP performance.

Research paper thumbnail of High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics

ICSP 2004: International Conference on Signal …, Jan 1, 2004

High Speed Efficient NXN Bit Parallel Hierarchical Overlay Multiplier ArchitectureBased On Ancien... more High Speed Efficient NXN Bit Parallel Hierarchical Overlay Multiplier ArchitectureBased On Ancient Indian Vedic Mathematics. Himanshu Thapliyal, MB Srinivas ICSP 2004: International Conference on Signal Processing, 2004. ...

Research paper thumbnail of High speed energy efficient ALU design using Vedic multiplication techniques

… Tools for Engineering …, Jan 1, 2009

Abstract—The ever increasing demand in enhancing the ability of processors to handle the complex ... more Abstract—The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced ...

Research paper thumbnail of A High Speed Block Convolution using Ancient Indian Vedic Mathematics

Conference on …, Jan 1, 2007

In Digital Signal Processing applications, the convolution with a very long sequence is often req... more In Digital Signal Processing applications, the convolution with a very long sequence is often required. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) method can be considered. The OLA and OLS are well ...

Research paper thumbnail of The Implementation of Vedic Algorithms in Digital Signal Processing

Global J. of Engng. Educ, Jan 1, 2004

Research paper thumbnail of Implementation of Vedic Multiplier For Digital Signal Processing

… conference on VLSI …, Jan 1, 2011

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast mult... more Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms, etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. The whole of Vedic mathematics is based on 16 sutras (word formulae) and manifests a unified structure of mathematics. Among the various methods of multiplication in Vedic mathematics, Urdhava tiryakbhyam is discussed in detail. Urdhava tiryakbhyam is the general multiplication formula applicable to all cases of multiplication. The coding is done in VHDL (very high speed integrated circuit hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after the synthesis is compared with normal multiplier. Further, this Vedic multiplier is used in matrix multiplication. This Vedic multiplier can bring great improvement in the DSP performance.

Research paper thumbnail of High Speed Efficient N x N Bit Parallel Hierarchical Overlay Multiplier Architecture Based on Ancient Indian Vedic Mathematics

ICSP 2004: International Conference on Signal …, Jan 1, 2004

High Speed Efficient NXN Bit Parallel Hierarchical Overlay Multiplier ArchitectureBased On Ancien... more High Speed Efficient NXN Bit Parallel Hierarchical Overlay Multiplier ArchitectureBased On Ancient Indian Vedic Mathematics. Himanshu Thapliyal, MB Srinivas ICSP 2004: International Conference on Signal Processing, 2004. ...

Research paper thumbnail of High speed energy efficient ALU design using Vedic multiplication techniques

… Tools for Engineering …, Jan 1, 2009

Abstract—The ever increasing demand in enhancing the ability of processors to handle the complex ... more Abstract—The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced ...

Research paper thumbnail of A High Speed Block Convolution using Ancient Indian Vedic Mathematics

Conference on …, Jan 1, 2007

In Digital Signal Processing applications, the convolution with a very long sequence is often req... more In Digital Signal Processing applications, the convolution with a very long sequence is often required. In order to compute convolution of long sequence, Overlap-Add method (OLA) and Overlap-Save method (OLS) method can be considered. The OLA and OLS are well ...

Research paper thumbnail of The Implementation of Vedic Algorithms in Digital Signal Processing

Global J. of Engng. Educ, Jan 1, 2004

Log In