Ali Chehab - American University of Beirut (original) (raw)

Papers by Ali Chehab

HAL (Le Centre pour la Communication Scientifique Directe), 2019

Microelectronics Reliability, Sep 1, 2018

Common problems with Oxide-based Resistive RAM are related to high variability in operating condi... more Common problems with Oxide-based Resistive RAM are related to high variability in operating conditions and high programming currents during FORMING, SET and RESET operations. Although research has taken steps to resolve these issues, variability combined with high programming currents remains an important characteristic for RRAMs. In a conventional write scheme with fixed duration and amplitude, the programming current is not controlled, which degrades the cell performance (power consumption and variability) due to over-programming. In this paper, a self-adaptive write driver is proposed to control the write current. A feedback mechanism based on current comparison is used to switch off the write stimulus as soon as the preferred write current is reached. Compared to conventional write schemes, in the proposed write-assist circuit, the write energy per bit is reduced by 27% and the standard deviation of post-FORMING distributions is reduced by 57%.

arXiv (Cornell University), Dec 5, 2017

IEEE Communications Letters, 2017

Mobile Networks and Applications, Oct 24, 2018

Physical Layer Security (PLS) has emerged as a promising solution for small and resource-limited ... more Physical Layer Security (PLS) has emerged as a promising solution for small and resource-limited wireless communications devices, to reduce the overhead associated with the required security resources and latency. In contrast to traditional security schemes, PLS relies on and benefits from the random nature of physical channels. However, the majority of PLS schemes in the literature lack the notion of secrecy and dynamicity, and employ static keys to generate fixed cipher primitives. In this paper, a dynamic key generation scheme that combines a pre-shared/stored secret key with a dynamic nonce extracted from channel information (for each new session) is proposed. The main advantage of this approach is that it achieves a highsecurity level with minimal overhead. Moreover, the obtained dynamic key can be changed frequently upon any change in channel parameters. Using the produced dynamic keys, cipher primitives are generated (permutation operations), which get updated for each frame symbol. This process ensures different and unique encryption layers for each new input frame and for each symbol in the input frame. Equally important, the proposed encryption algorithm operates at the modulation symbol level in order to attain performance by limiting the effect of error propagation and by realizing parallel encryption/decryption for each frame symbol. In addition, a preamble encryption scheme is also proposed to prevent unauthorized synchronization or channel estimation by illegitimate users. The security level of the proposed cipher scheme mainly depends on a secret key and the dynamicity of the channel to update the cipher primitives used for each frame symbol. Finally, security and performance analyses validate the efficiency and the robustness of the proposed approach.

Journal of Signal Processing Systems, Mar 13, 2017

Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

2017 XXXIInd General Assembly and Scientific Symposium of the International Union of Radio Science (URSI GASS)

Fast Statistical Analysis Using Machine Learning

Machine Learning in VLSI Computer-Aided Design, 2019

In this chapter, we describe a fast statistical yield analysis methodology for memory design. At ... more In this chapter, we describe a fast statistical yield analysis methodology for memory design. At the heart of its engine is a mixture importance sampling-based methodology which comprises a uniform sampling stage and an importance sampling stage. Logistic regression-based machine learning techniques are employed for modeling the circuit response and speeding up the importance sample points simulations. To avoid overfitting, we rely on a cross-validation-based regularization framework for ordered feature selection. The methodology is comprehensive and computationally efficient. We demonstrate the methodology on an industrial state-of-the-art 14 nm FinFET SRAM design with write-assist circuitry. The results corroborate well with hardware and with the fully circuit-simulation-based approach.

S-DES: An efficient & secure DES variant

2018 IEEE Middle East and North Africa Communications Conference (MENACOMM), 2018

In this paper, we propose an efficient and secure variant of DES (S-DES), which strikes a good ba... more In this paper, we propose an efficient and secure variant of DES (S-DES), which strikes a good balance between performance and security level when compared to 3DES. S- DES is based on the same round function of DES, however, we introduce different modifications to overcome the weaknesses of the original DES such as the extended Feistel Network (FN) instead of the FN. The main advantage of the proposed scheme is that it benefits from the cryptographic characteristics of DES substitution and diffusion primitives. However, the size of the secret key is extended to 112 bits and the data block is set to 128 bits, which provides better resistance against the attacks that plagued DES. Moreover, the proposed internal scheme of S-DES allows for a parallel implementation, which reduces the response latency. Finally, the main idea of this paper is not to provide a better alternative to the existing standard (AES), but to provide an efficient candidate solution from the well-optimized DES cipher.

Virtualized network views for localizing misbehaving sources in SDN data planes

2017 IEEE International Conference on Communications (ICC), 2017

In this paper, we present VISKA, a Cloud security service for detecting malicious switching eleme... more In this paper, we present VISKA, a Cloud security service for detecting malicious switching elements in software defined networking (SDN) environments. VISKA leverages network virtualization and secure probabilistic sketching to isolate misbehaving switches in the underlying SDN network data plane. The main contribution lies in utilizing network virtualization in SDN environments to dynamically isolate parts of the data plane and check their forwarding behavior. This is achieved by applying a set of focused packet probing and sketching mechanisms on virtualized network views mapped to these data plane partitions instead of focusing the security mechanisms on the whole physical network. VISKA flexibly analyzes the network behavior of the granular virtual views and recursively partitions these views to reduce the problem size in order to localize abnormal/malicious network switching units. A test bed prototype implementation is realized on the OpenVirtex SDN network virtualization platform. The experimental analysis corroborated the algorithm's convergence property using the linear and FatTree topologies with SDN network sizes of up to 250 switching units.

Regularized logistic regression for fast importance sampling based SRAM yield analysis

2017 18th International Symposium on Quality Electronic Design (ISQED), 2017

In this paper, we propose a fast logistic regression based importance sampling methodology with o... more In this paper, we propose a fast logistic regression based importance sampling methodology with ordered feature selection to avoid overfitting and enable regularization. We rely on the importance region search simulations to build a regularized logistic regression model that is capable of accurately predicting pass fail criteria for purposes of yield analysis stage. We also propose a cross-validation-based regularization framework for ordered feature selection. We prove the efficiency of the proposed methodology by analyzing state-of-the-art FinFET SRAM designs. The proposed methodology is comprehensive and computationally efficient resulting in high-fidelity models. We report on average around 4.5% false prediction rate for the importance sample points prediction. This translates into accurate yield prediction for the rare fail events. All this comes at significant savings in runtime.

A Multi-Gbps Fully Pipelined Layered Decoder for IEEE 802.11n/ac/ax LDPC Codes

2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2017

This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC c... more This paper presents a fully pipelined layered decoder architecture for IEEE 802.11 n/ac/ax LDPC codes, free of idle cycles. Several decoder architectures for such codes have emerged in the literature featuring throughputs in the multi- Gbps range. The proposed architecture surpasses the highest reported throughput for IEEE 802.11 n/ac/ax LDPC codes. This is achieved 1) algorithmically, by implementing the layered LDPC decoding schedule, and 2) architecturally, by optimizing register-based memories for IEEE 802.11n/ac LDPC codes and implementing an idle-cycle-free pipelined single-codeword datapath decoder. Register-based memories provide full bandwidth access to read and write all messages of a layer in one clock cycle. Single-codeword processing in the datapath significantly reduces memory overhead compared to other architectures that process multiple codewords to boost throughput at the expense of a larger footprint. The proposed architecture is synthesized in 40 nm CMOS process for IEEE 802.11 n/ac, rate 1/2 LDPC codes. The decoder occupies an area of 0.38 mm2, runs at a frequency of 780 MHz, and achieves a throughput of 4.2 Gbps.

Efficient and Secure Physical Encryption Scheme for Low-Power Wireless M2M Devices

2018 14th International Wireless Communications & Mobile Computing Conference (IWCMC), 2018

Recently, physical layer security has emerged as a promising security scheme for wireless network... more Recently, physical layer security has emerged as a promising security scheme for wireless networks, in contrast to traditional solutions that mainly rely on upper network layers. As such, several physical layer encryption algorithms that benefit from the random characteristics of physical channels have appeared in the literature. However, the majority of these schemes lack the notion of secrecy and dynamicity. In this paper, we focus on enhancing the physical layer encryption for wireless machine-to-machine devices, which share the same channel, with the aim of striking a good balance between performance and security robustness. The main idea is to perform encryption at the physical layer after symbol modulation. The cipher scheme is based on one round and one operation that reduces the encryption overhead in terms of latency and required resources. Furthermore, we propose a dynamic key approach that combines a pre-shared/stored secret key with a dynamic nonce extracted from the channel information to generate a dynamic key. The main advantage of the dynamic key approach is that it achieves a high-security level with minimal overhead. The dynamic key can be changed frequently upon any change in channel parameters or upon starting a new session. In addition to data encryption, a preamble encryption scheme is also proposed to prevent unauthorized synchronization or channel estimation by illegitimate users. Finally, security and performance analyses are performed to demonstrate the validity, efficiency and robustness of the proposed approach.

Oxide-based RRAM models for circuit designers: A comparative analysis

2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), 2017

Recently, Oxide-based random access memory devices (OxRAM) have shown the potential to outperform... more Recently, Oxide-based random access memory devices (OxRAM) have shown the potential to outperform non-volatile memories due to their high scalability, high-speed, high-density, and low-energy operation. A critical requirement for using OxRAM at circuit level is a predictive model for device behavior that can be used in simulations, as well as a guide for circuit designers. The proper choice of the memory device model leads to a better understanding of the memory cell behavior, and also to a better exploitation of its unique properties in novel systems. This work is intended to help designers decide on the most appropriate memory cell model for circuit design. We present a comparative study of the different major existing OxRAM models tested within the same simulation environment.

IEEE Transactions on Communications, 2018

Multimedia Tools and Applications, 2018

Efficient Chaotic Encryption Scheme with OFB Mode

International Journal of Bifurcation and Chaos, 2019

Data confidentiality is mandatory during transmission or when storing sensitive information, espe... more Data confidentiality is mandatory during transmission or when storing sensitive information, especially in financial, medical and military applications. In this context, several cipher solutions and techniques have been presented in the literature. However, existing solutions are mainly based on static structures, where the confusion and diffusion primitives are fixed and independent of the secret key. In this article, we propose a new block cipher scheme that is based on the Substitution Permutation Networks (SPN). The proposed cipher consists of three operations: round-key addition, substitution, and bits’ permutation. Moreover, the substitution operation is applied at the byte level and it is based on a dynamically generated S-box, while the diffusion primitives are applied at the bit level using a dynamically generated P-box. Such key-dependent design ensures better cryptographic strength and system performance when compared, for instance, to DES, 3DES, RC5, and PRESENT schemes,...