T. Alexoudi | Aristotle University of Thessaloniki (original) (raw)
Papers by T. Alexoudi
IEEE Photonics Journal, 2013
An optical RAM row access gate followed by a column address selector for wavelength-division-mult... more An optical RAM row access gate followed by a column address selector for wavelength-division-multiplexing (WDM)-formatted words employing a single semiconductor optical amplifierVMach-Zehnder interferometer (SOA-MZI) is presented. RAM row access is performed by the SOA-MZI that grants random access to a 4-bit WDM-formatted optical word employing multiwavelength cross-phase-modulation (XPM) phenomena, whereas column decoding is carried out in a completely passive way using arrayed waveguide grating. Proof-of-concept experimental verification for both positive and negative logic access is demonstrated for 4 Â 10 Gb/s optical words, showing error-free operation with only 0.4-dBpeak-power penalty and requiring a power value of 25 mW/Gb/s.
Optical Components and Materials X, 2013
ABSTRACT Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of elec... more ABSTRACT Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOA-based multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multi-wavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bitchannels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.
2013 15th International Conference on Transparent Optical Networks (ICTON), 2013
ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owe... more ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work on optical RAM cell configurations exploiting silicon-based integrated switching and latching elements with SOAs serving as the active devices. We review both their experimental and underlying theoretical framework and proceed with the demonstration of new optical cache architectural paradigms enabled by the introduction of WDM principles in the storage area. The higher than 40GHz optical RAM cell operational speeds and the WDM-enabled cache architectures comprise two major factors towards realizing ultra-fast and low-power CPU-memory communication.
IEEE Photonic Society 24th Annual Meeting, 2011
ABSTRACT We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical... more ABSTRACT We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical T-Flip-Flop that employs one SOA-MZI and a feedback loop. Experimental verification is demonstrated at 8MHz using a fiber-based feedback loop implementation.
IEEE Photonics Journal, 2012
We demonstrate a detailed theoretical and experimental analysis of the deterministic timing jitte... more We demonstrate a detailed theoretical and experimental analysis of the deterministic timing jitter induced on intensity-modulated optical pulse streams when propagating through a SOA. The mathematical analysis reveals an approximate linear relationship between jitter and pulse intensity modulation when the SOA gain recovery time is shorter than the pulse period. The theoretical results have been confirmed by experimental deterministic timing jitter measurements for intensity modulation levels up to 8 dB, showing good agreement between theory and experiment.
37th European Conference and Exposition on Optical Communications, 2011
ABSTRACT We present an all-optical T flip-flop that requires a single toggling driving signal and... more ABSTRACT We present an all-optical T flip-flop that requires a single toggling driving signal and is based on a SOA-MZI and a feedback loop. Experimental proof-of-principle verification is demonstrated at 7.969 Mb/s using a fiber-based feedback implementation.
IEEE Photonics Technology Letters, 2000
The authors demonstrate a novel all-optical T-flip-flop (TFF) layout utilizing a single optical l... more The authors demonstrate a novel all-optical T-flip-flop (TFF) layout utilizing a single optical latching element that comprises an integrated semiconductor optical amplifier and Mach-Zehnder inteferometer and a feedback loop. Experimental proof-of-concept verification is presented at 8 Mb/s using off-the-shelf bulk components and a fiber-based feedback implementation. The proposed TFF architecture requires the minimum number of active components and just a single toggling signal as input. Its simple circuit design is amenable with photonic integration and holds the credentials for operation at multi-Gb/s speeds.
ABSTRACT We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS)... more ABSTRACT We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS) circuits for use as optical static RAM (SRAM) bank peripherals in future optical cache memory implementations. We show that the introduction of the wavelength dimension in both the memory address and data word fields can lead to RAS and CAS architectures that rely exclusively on all-passive wavelength-selective configurations. An all-optical 2 × 4 RAS comprising a wavelength-selective filtering matrix (λ-matrix) and a wavelength-based CAS unit formed by a simple AWG element are demonstrated in proof-of-principle experiments at 10 Gb/s with error-free operation at 10 -9 BER value using two different types of WDM SRAM row Access Gate (AG): a cross-phase modulation SOA-MZI gate and a single SOA cross-gain modulation gate, with the first providing the higher performance compared to SOA module and the second offering lower power requirements between the two WDM AG. A chip-scale optical cache peripheral circuitry development path using Silicon-on-Insulator (SOI) ring resonators for the λ-matrix implementation is also presented and the proposed architecture is evaluated via physical layer simulations using SOAs as SRAM row AGs at 10 Gb/s for a 16×4 optical SRAM bank. Moreover, we discuss on possible improvements towards reducing insertion losses of the RAS/CAS modules in order to allow for increased block sizes. Finally, we provide a detailed analysis on the design and parameter specifications required for RAS and CAS block size scaling towards supporting higher-capacity optical SRAM banks.
IEEE Photonics Technology Letters, 2000
ABSTRACT In this letter, we present new architectural perspectives in optical static RAM configur... more ABSTRACT In this letter, we present new architectural perspectives in optical static RAM configurations by exploiting the wavelength dimension in address domain. We present a 2$,times,$4 optical RAM row decoder (RD) that relies its operation on an all-passive wavelength-selective filtering matrix ($lambda$-matrix), receiving WDM-formatted address bits (Wordline) as input. The 2$,times,$4 RD is followed by an semiconductor optical amplifier Mach–Zehnder interferometer access gate and a column decoding unit to provide complete optical RAM row access. Proof-of-concept experimental verification of a 2$,times,$ 4 optical RAM RD is shown at 10 Gb/s, providing error-free operation with a peak power penalty lower than 0.2 dB.
IEEE Photonics Journal, 2013
An optical RAM row access gate followed by a column address selector for wavelength-division-mult... more An optical RAM row access gate followed by a column address selector for wavelength-division-multiplexing (WDM)-formatted words employing a single semiconductor optical amplifierVMach-Zehnder interferometer (SOA-MZI) is presented. RAM row access is performed by the SOA-MZI that grants random access to a 4-bit WDM-formatted optical word employing multiwavelength cross-phase-modulation (XPM) phenomena, whereas column decoding is carried out in a completely passive way using arrayed waveguide grating. Proof-of-concept experimental verification for both positive and negative logic access is demonstrated for 4 Â 10 Gb/s optical words, showing error-free operation with only 0.4-dBpeak-power penalty and requiring a power value of 25 mW/Gb/s.
Optical Components and Materials X, 2013
ABSTRACT Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of elec... more ABSTRACT Optical RAM has emerged as a promising solution for overcoming the “Memory Wall” of electronics, indicating the use of light in RAM architectures as the approach towards enabling ps-regime memory access times. Taking a step further towards exploiting the unique wavelength properties of optical signals, we reveal new architectural perspectives in optical RAM structures by introducing WDM principles in the storage area. To this end, we demonstrate a novel SOA-based multi-wavelength Access Gate for utilization in a 4x4 WDM optical RAM bank architecture. The proposed multi-wavelength Access Gate can simultaneously control random access to a 4-bit optical word, exploiting Cross-Gain-Modulation (XGM) to process 8 Bit and Bitchannels encoded in 8 different wavelengths. It also suggests simpler optical RAM row architectures, allowing for the effective sharing of one multi-wavelength Access Gate for each row, substituting the eight AGs in the case of conventional optical RAM architectures. The scheme is shown to support 10Gbit/s operation for the incoming 4-bit data streams, with a power consumption of 15mW/Gbit/s. All 8 wavelength channels demonstrate error-free operation with a power penalty lower than 3 dB for all channels, compared to Back-to-Back measurements. The proposed optical RAM architecture reveals that exploiting the WDM capabilities of optical components can lead to RAM bank implementations with smarter column/row encoders/decoders, increased circuit simplicity, reduced number of active elements and associated power consumption. Moreover, exploitation of the wavelength entity can release significant potential towards reconfigurable optical cache mapping schemes when using the wavelength dimension for memory addressing.
2013 15th International Conference on Transparent Optical Networks (ICTON), 2013
ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owe... more ABSTRACT The processor-memory performance gap, commonly referred to as “Memory Wall” problem, owes to the speed mismatch between processor and electronic RAM clock frequencies. In that perspective, optical RAMs storing and retrieving information in the form of light with ps-scale memory access times seem to hold the potential for replacing small-size caches, offering at the same time a cache memory system being fully-compatible with optically interconnected CPU-memory architectures. In this article, we present our recent work on optical RAM cell configurations exploiting silicon-based integrated switching and latching elements with SOAs serving as the active devices. We review both their experimental and underlying theoretical framework and proceed with the demonstration of new optical cache architectural paradigms enabled by the introduction of WDM principles in the storage area. The higher than 40GHz optical RAM cell operational speeds and the WDM-enabled cache architectures comprise two major factors towards realizing ultra-fast and low-power CPU-memory communication.
IEEE Photonic Society 24th Annual Meeting, 2011
ABSTRACT We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical... more ABSTRACT We present a 3-bit all-optical counter comprising two cascaded stages of a novel optical T-Flip-Flop that employs one SOA-MZI and a feedback loop. Experimental verification is demonstrated at 8MHz using a fiber-based feedback loop implementation.
IEEE Photonics Journal, 2012
We demonstrate a detailed theoretical and experimental analysis of the deterministic timing jitte... more We demonstrate a detailed theoretical and experimental analysis of the deterministic timing jitter induced on intensity-modulated optical pulse streams when propagating through a SOA. The mathematical analysis reveals an approximate linear relationship between jitter and pulse intensity modulation when the SOA gain recovery time is shorter than the pulse period. The theoretical results have been confirmed by experimental deterministic timing jitter measurements for intensity modulation levels up to 8 dB, showing good agreement between theory and experiment.
37th European Conference and Exposition on Optical Communications, 2011
ABSTRACT We present an all-optical T flip-flop that requires a single toggling driving signal and... more ABSTRACT We present an all-optical T flip-flop that requires a single toggling driving signal and is based on a SOA-MZI and a feedback loop. Experimental proof-of-principle verification is demonstrated at 7.969 Mb/s using a fiber-based feedback implementation.
IEEE Photonics Technology Letters, 2000
The authors demonstrate a novel all-optical T-flip-flop (TFF) layout utilizing a single optical l... more The authors demonstrate a novel all-optical T-flip-flop (TFF) layout utilizing a single optical latching element that comprises an integrated semiconductor optical amplifier and Mach-Zehnder inteferometer and a feedback loop. Experimental proof-of-concept verification is presented at 8 Mb/s using off-the-shelf bulk components and a fiber-based feedback implementation. The proposed TFF architecture requires the minimum number of active components and just a single toggling signal as input. Its simple circuit design is amenable with photonic integration and holds the credentials for operation at multi-Gb/s speeds.
ABSTRACT We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS)... more ABSTRACT We demonstrate WDM-enabled all-passive optical row and column address selector (RAS/CAS) circuits for use as optical static RAM (SRAM) bank peripherals in future optical cache memory implementations. We show that the introduction of the wavelength dimension in both the memory address and data word fields can lead to RAS and CAS architectures that rely exclusively on all-passive wavelength-selective configurations. An all-optical 2 × 4 RAS comprising a wavelength-selective filtering matrix (λ-matrix) and a wavelength-based CAS unit formed by a simple AWG element are demonstrated in proof-of-principle experiments at 10 Gb/s with error-free operation at 10 -9 BER value using two different types of WDM SRAM row Access Gate (AG): a cross-phase modulation SOA-MZI gate and a single SOA cross-gain modulation gate, with the first providing the higher performance compared to SOA module and the second offering lower power requirements between the two WDM AG. A chip-scale optical cache peripheral circuitry development path using Silicon-on-Insulator (SOI) ring resonators for the λ-matrix implementation is also presented and the proposed architecture is evaluated via physical layer simulations using SOAs as SRAM row AGs at 10 Gb/s for a 16×4 optical SRAM bank. Moreover, we discuss on possible improvements towards reducing insertion losses of the RAS/CAS modules in order to allow for increased block sizes. Finally, we provide a detailed analysis on the design and parameter specifications required for RAS and CAS block size scaling towards supporting higher-capacity optical SRAM banks.
IEEE Photonics Technology Letters, 2000
ABSTRACT In this letter, we present new architectural perspectives in optical static RAM configur... more ABSTRACT In this letter, we present new architectural perspectives in optical static RAM configurations by exploiting the wavelength dimension in address domain. We present a 2$,times,$4 optical RAM row decoder (RD) that relies its operation on an all-passive wavelength-selective filtering matrix ($lambda$-matrix), receiving WDM-formatted address bits (Wordline) as input. The 2$,times,$4 RD is followed by an semiconductor optical amplifier Mach–Zehnder interferometer access gate and a column decoding unit to provide complete optical RAM row access. Proof-of-concept experimental verification of a 2$,times,$ 4 optical RAM RD is shown at 10 Gb/s, providing error-free operation with a peak power penalty lower than 0.2 dB.