Mohammad Najmzadeh - Profile on Academia.edu (original) (raw)

Papers by Mohammad Najmzadeh

Applied Physics Express, 2016

In this paper, a multilayer ReS p-n homojunction is fabricated on an oxidized Si substrate, and i... more In this paper, a multilayer ReS p-n homojunction is fabricated on an oxidized Si substrate, and its photoemission under a forward bias and its photodetection under a reverse bias are reported for the first time. Au nanoparticles were used to make lateral p-n homojunctions. The device shows room temperature photoemission in the IR range, and in the photodetector mode, it shows a 0.41 A/W responsivity under illumination by a 660 nm red laser.

2015 73rd Annual Device Research Conference (DRC), 2015

SSE2012-Special interest to the engineering community research highlight by Advances in Engineering - 2012

A top-down Si nanowire platform is developed to make dense array of gate-all-around (GAA) Si nano... more A top-down Si nanowire platform is developed to make dense array of gate-all-around (GAA) Si nanowire MOSFETs with scalable nanowire cross-section down to 4 nm on a SOI substrate. High level of local uniaxial stress (both tensile and compressive) can be integrated to this Si nanowire platform using e.g. metal gate strain and local oxidation to boost the carrier mobility. Nanowire pattern transfer to the wafer in the presence of hard mask, Si nanowire side-wall engineering by anisotropic dry Si etching (HBr/O2) to shrink further the cross-section, stress-limited oxidation and ALD high-k/metal gate stack are the key process steps. A high level of uniaxial tensile stress (up to 5.6 GPa) is estimated in the buckled GAA Si nanowires based on a Gaussian buckling profile assumption, using top and tilted-view nanowire SEM pictures. Indeed, a significant stress level modulation (~1.2 to 5.6 GPa) is reported by the Si nanowire width modulation (44 to 4 nm) at a constant nanowire length (2 μm)...

Najmzadeh-ULIS2013-poster

The precision of carrier mobility extraction in a JAM device strongly depends on the doping level... more The precision of carrier mobility extraction in a JAM device strongly depends on the doping level in the S/D extensions. The bias-dependency of several key MOSFET parameters (e.g. gate-channel capacitance, effective channel width and series resistance) together with the non-linear mobile charge accumulation in the channel due to the corners in the GAA Si nanowires, with cross-section down to 5 nm, and their impacts on the carrier mobility extraction are addressed in details for the first time.

Najmzadeh-MicroTAS2007-poster

The resonance frequency of a suspended fluid-conveying Si micro-tube bridge resonator depends on ... more The resonance frequency of a suspended fluid-conveying Si micro-tube bridge resonator depends on its mass, which is a function of the density of the fluid inside the suspended bridge Si micro-tube.

IEEE Transactions on Nanotechnology, 2015

A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET,... more A type-III (broken gap) band alignment heterojunction vertical in-line InAs/AlSb/GaSb tunnel FET, including a 2-nmthin AlSb tunneling barrier is demonstrated. The impact of overlap and underlap gate is studied experimentally and supported further by quasi-stationary 2-D TCAD Sentaurus device simulations. Hydrogen silsesquioxane is used as a novel mechanical support structure to suspend the 10-nm-thin InAs drain with enough undercut to be able to demonstrate an overlap gate architecture. The overlap gate InAs/AlSb/GaSb TFET shows an ON current density of 22 μA/μm 2 at V G S = V D S = 0.4 V and the subthreshold slope is 194 mV/decade at room temperature and 46 mV/decade at 100 K.

In this paper, we report for the first time, assessment on mobility extraction in equilateral tri... more In this paper, we report for the first time, assessment on mobility extraction in equilateral triangular gate-all-around Si nanowire junctionless (JL) nMOSFETs with cross-section down to 5 nm. This analysis was performed in accumulation regime, as a first step, addressing bias dependency of various key MOSFET parameters (e.g. series resistance, channel width and gate-channel capacitance), non uniform electron density due to corners and quantization. A significant bias-dependent series resistance variation in JL MOSFETs is reported above flat-band, leading to a significant mobility extraction accuracy drop of �50%. All quasistationary device simulations were done on 100 nm long channel devices with 5-20 nm NW width, 2 nm Si0 2 gate oxide thickness and 1x10 19 cm-3 n-type channel doping using a constant mobility model (100 cm 2 /V•s).

Solid-State Electronics, 2010

This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature impr... more This paper reports all-silicon asymmetrically strained Tunnel FET architectures that feature improved subthreshold swing and I on /I off characteristics. We demonstrate that a lateral strain profile corresponding to at least 0.2 eV band-gap shrinkage at the BTB source junction could act as an optimized performance Tunnel FET enabling the cancellation of the drain threshold voltage. To implement a real device, we demonstrate using GAA Si NW with asymmetric strain profile using two local stressor technologies to have >4-5 GPa peak of lateral uniaxial tensile stress in the Si NW.

Microelectronic Engineering, 2010

In this work we present for the first time correlation of lateral uniaxial tensile strain and I-V... more In this work we present for the first time correlation of lateral uniaxial tensile strain and I-V characteristics of GAA Si NW n-MOSFET, all measured on the same device. Micro-Raman spectroscopy is employed for direct strain measurement on devices to exploit the main sources of process-induced strain, found to be accumulation of mechanical potential energy in the Si NWs during local oxidation and releasing it in the form of local lateral uniaxial tensile stress in the Si NW by out-of-plane mechanical buckling as well as lateral in-plane elongation during stripping the hard mask and the grown oxide. A triangular GAA Si NW with 0.6 GPa peak of lateral uniaxial tensile stress, fabricated using this bulk top-down technology, exhibits promising improvements e.g. of the normalized drain current (I D =W eff) up to 38%, of the transconductance (g m =W eff) up to 50%, of the low field mobility by 53% with a peak of 64% in the peak stress region, compared to a reference device. The mobility extraction originally takes into account the measured strain profile in the channel.

Microelectronic Engineering, 2009

In this paper, we investigate the effect of different process parameters on oxidation-induced str... more In this paper, we investigate the effect of different process parameters on oxidation-induced strain (OIS) into a doubly-clamped silicon nanowire FET to control and finally, enhance carrier mobility. Spacer technology together with sacrificial thermal oxidation were used to fabricate %100 nm wide Si NWs. The built-in tensile stress in the Si NWs was measured using micro-Raman spectroscopy and a maximum of 2.6 GPa was found.

Journal of Micromechanics and Microengineering, 2007

In this paper, a micromachined silicon straight tube is tested as a fluid density sensor. In comp... more In this paper, a micromachined silicon straight tube is tested as a fluid density sensor. In comparison with other density measurement techniques, the use of micromachined tubes require small sample volumes and allows continuous monitoring of the fluid density in microfluidic systems. Different vibration modes of the sensor were detected and calibrated using a laser Doppler vibrometer (LDV). Linearity, simplicity, the straightforward fabrication and evaluation, the low flow restriction and reduced risk of trapping gas in the sensor due the absence of corners are the design's main advantages. The ability of the sensor to measure density of multiphase fluids and provide accurate results independent of other fluid parameters, allows it to be used in varying fields such as the biomedical, pharmaceutical and petrochemical industries.

IEEE Transactions on Electron Devices, 2010

This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA... more This work demonstrates a method for incorporating strain in silicon nanowire gate-all-around (GAA) n-MOSFETs by oxidation-induced bending of the nanowire channel and reports on the resulting improvement in device performance. The variation in strain measured during processing is discussed. The strain profile in silicon nanowires is evaluated by Raman spectroscopy both before device gate stack fabrication (tensile strains of up to 2.5% are measured) and by measurement through the polysilicon gate on completed electrically characterized devices. Drain current boosting in bended n-channels is investigated as a function of the transistor operation regime, and it is shown that the enhancement depends on the effective electrical field. The maximum observed electron mobility enhancement is on the order of 100% for a gate bias near the threshold voltage. Measurements of stress through the full gate stack and experimental device characteristics of the same transistor reveal a stress of 600 MPa and corresponding improvements of the normalized drain current, normalized transconductance, and low-field mobility by 34% (at maximum gate overdrive), 50% (at g max), and 53%, respectively, compared with a reference nonstrained device at room temperature. Finally, it is found that, at low temperatures, the low-field mobility is much higher in bended devices, compared with nonbended devices.

IEEE Transactions on Nanotechnology 2012-Vol 11-Front-Cover

About the cover: Top-view SEM micrograph of a multi-gate dual Si nanowire MOSFET on bulk Si. The ... more About the cover: Top-view SEM micrograph of a multi-gate dual Si nanowire MOSFET on bulk Si. The in-plane nanowire buckling is a sign of uniaxial tensile stress in the channel. The arrow indicates the scan axis and direction of the laser spot in the micro-Raman measurement.

Abstract—In this paper, we report, for the first time, corner effect analysis in the gate-all-aro... more Abstract—In this paper, we report, for the first time, corner effect analysis in the gate-all-around equilateral triangular silicon nanowire (NW) junctionless (JL) nMOSFETs, from subthreshold to strong accumulation regime. Corners were found to accumulate and deplete more electrons than the flat sides or the channel center, when above (local accumulation) and below (local depletion) the flat-band voltage, respectively. On the contrary to the corner effect in the inversion mode (IM) devices, there is no major contribution of corners in the subthreshold current, and therefore, there is no subthreshold device behavior degradation (only one threshold voltage in the system). N-type channel doping levels of 1 × 10 19,5 × 10 18,and1 × 10 18 cm−3 were used for quasi-stationary device simulations of JL and AM MOSFETs, and corner effect was studied for 5, 10, and 15 nm wide equilateral triangular Si NW MOSFETs with a 2 nm SiO2 gate oxide thickness (VDS = 0V;T = 300 K). While the local quantum...

Keywords: Si nanowire ; Strain engineering ; Local oxidation ; Uniaxial tensile stress ; CMOS boo... more Keywords: Si nanowire ; Strain engineering ; Local oxidation ; Uniaxial tensile stress ; CMOS booster Reference NANOLAB-CONF-2008-017 Record created on 2009-07-15, modified on 2017-05-10

Keywords: Straight Si tube ; Fluid-conveying Si microtube ; Bridge resonator ; Fluid density sens... more Keywords: Straight Si tube ; Fluid-conveying Si microtube ; Bridge resonator ; Fluid density sensor ; Microfluidic Reference EPFL-CONF-175287 URL: http://www.cbmsociety.org/conferences/microtas2007/ Record created on 2012-03-01, modified on 2017-05-10

As a first step, I would like to thank Swiss Federal Institute of Technology in Lausanne-EPFL, th... more As a first step, I would like to thank Swiss Federal Institute of Technology in Lausanne-EPFL, the EDMI doctoral school and the Nanoelectronic Devices Laboratory (Nanolab) for doing this thesis in a competitive basis. It was a good opportunity to gain several knowledge in this thesis supported by extensive course works in microsystems and microelectronics as well, organized by EPFL, FSRM and MEAD Education SA. Thanks to Dr. Yoshishige Tsuchiya and Sheng Ye at Southampton University, UK, for the micro-Raman measurements (using a TERS setup) on deeply scaled cross-section Si nanowires and Dr.

Ultra low power nanowire FETs and Tunnel FETs

L. Lattanzio, L. De Michielis, M. Najmzadeh, A.M. Ionescu, Nano Tech (the world's largest ex... more L. Lattanzio, L. De Michielis, M. Najmzadeh, A.M. Ionescu, Nano Tech (the world's largest exhibition on nanotechnology), Tokyo, Japan, 2011 (poster; promoted by the Swiss Embassy in Japan at the Swiss Pavilion).

IEEE Transactions on Nanotechnology - Vol 11 - 2012 - Front cover research highlight

Applied Physics Express, 2016

2015 73rd Annual Device Research Conference (DRC), 2015

SSE2012-Special interest to the engineering community research highlight by Advances in Engineering - 2012

Najmzadeh-ULIS2013-poster

Najmzadeh-MicroTAS2007-poster

IEEE Transactions on Nanotechnology, 2015

Solid-State Electronics, 2010

Microelectronic Engineering, 2010

Microelectronic Engineering, 2009

Journal of Micromechanics and Microengineering, 2007

IEEE Transactions on Electron Devices, 2010

IEEE Transactions on Nanotechnology 2012-Vol 11-Front-Cover

Ultra low power nanowire FETs and Tunnel FETs

IEEE Transactions on Nanotechnology - Vol 11 - 2012 - Front cover research highlight

General rationale 1. Study 2D MOSFET operation of a fully-depleted bulk MoS 2 double-gate MOSFET ... more General rationale 1. Study 2D MOSFET operation of a fully-depleted bulk MoS 2 double-gate MOSFET at quasi-flatband back-gate for the first time (charge accumulation or depletion by the top-gate, V bg =0 V). 2. Perform I-V and C-V measurements considering an underlap top-gate architecture. 3. Extraction of carrier concentration and effective mobility, a complementary extraction method to the 6 probe Hall measurement. 4. Extraction of several key device parameters e.g. flatband voltage, dielectric constant and series resistance using I-V and C-V characteristics.

Multi-gate strained Si nanowires for ultra-low power MOSFETs

In this paper, 2D MOSFET operation of a fully-depleted double-gate bulk MoS 2 is studied at a qua... more In this paper, 2D MOSFET operation of a fully-depleted double-gate bulk MoS 2 is studied at a quasi-flatband of the back-gate for the first time. Several key device parameters such as equivalent oxide thickness (EOT), carrier concentration, flatband voltage, dielectric constant and carrier mobility were extracted from I-V and C-V characteristics and at room temperature. In a similar operation to the inversion-mode SOI MOSFETs in [1], the backgate was used to keep a sheet of mobile charges on the flake back-side by its quasi-flatband operation at a fixed voltage (0 V). Afterward, the top-gate was used as the active gate to perform mobile charge accumulation or depletion in the channel. shows the device architecture together with the high frequency R-C equivalent circuit model for this underlap gate architecture. represents the top-view microscope picture of the fabricated MoS2 bulk MOSFET with a flake thickness of 38 nm, measured by AFM. The fabrication steps include mechanical exfoliation of MoS 2 crystals on a 260 nm thick oxidized Si substrate, e-beam lithography to make S/D pads, 50 nm Ni by thermal evaporation and lift-off, gate patterning, high-k/metal-gate stack deposition (1 nm of SiO x by thermal evaporation, 11 nm of ZrO 2 by ALD deposition at 105 °C, 30 nm of Ni by thermal evaporation) and lift-off. The measurements were done at room temperature using an Agilent B1500A Semiconductor Parameter Analyzer. shows its I d -V g , reporting a subthreshold slope of 110 mV/dec. and I on /I off of ~1×10 5 , both at V ds =100 mV. EOT, dielectric constant, flatband voltage: depicts the C g -V g measurement between the top-gate and the sourcedrain electrodes (V ds =0 V) at a high frequency regime (1 MHz). In strong accumulation, the EOT numeric value of the gate stack can be extracted from the maximum value of gate-channel capacitance, resulting an EOT value of 6.3 nm. In the partial depletion regime, between threshold and flatband, the gate-channel capacitance would vary by

Gate-all-around buckled dual Si nanowire nMOSFETs on bulk Si for transport enhancement and digital logic application

Multi-gate architectures such as gate-all-around (GAA) Si nanowires are the promising candidates ... more Multi-gate architectures such as gate-all-around (GAA) Si nanowires are the promising candidates for aggressive CMOS downscaling due to the immunity to the issues regarding short channel effect, improved subthreshold slope and optimized power consumption. On the other hand, Si nanowires represent excellent mechanical properties e.g. yield strength of 10±2% [1] in comparison to 3.7% for bulk Si [2], a strong motivation to be used as interesting exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels [3]- or local band-gap modulation using >4 GPa uniaxial tensile stress in suspended Si channels to enhance band-to-band tunneling current in multi-gate Tunnel-FETs [6], all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels.

In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode... more In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOS-FETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm 2 /V.s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400 K and a VTH drift of -1.72 mV/K, VFB drift of -3.04 mV/K and an ion impurity scattering-based mobility reduction were observed.