John E. Savage | Brown University (original) (raw)
Books by John E. Savage
Papers by John E. Savage
15th Annual Symposium on Switching and Automata Theory (swat 1974), 1974
Advances in Mathematics, 1972
Internet governance is now an active topic of international discussion. Interest has been fueled ... more Internet governance is now an active topic of international discussion. Interest has been fueled by media attention to cyber crime, global surveillance, commercial espionage, cyber attacks, and threats to critical national infrastructures. Many nations have decided that they need more control over Internet-based technologies and the policies that support them. Others, emphasizing the positive aspects of these technologies, argue that traditional systems of Internet governance, which they label “multi-stakeholder” and which they associate with the success of the Internet, must continue to prevail.
Algebraic circuits combine operations drawn from an algebraic system. In this chapter we develop ... more Algebraic circuits combine operations drawn from an algebraic system. In this chapter we develop algebraic and combinatorial circuits for a variety of generally non-Boolean problems, including multiplication and inversion of matrices, convolution, the discrete Fourier transform, and sorting networks. These problems are used primarily to illustrate concepts developed in later chapters, so that this chapter may be used for reference when studying those chapters. For each of the problems examined here the natural algorithms are straight-line and the graphs are directed and acyclic; that is, they are circuits. Not only are straight-line algorithms the ones typically used for these problems, but in some cases they are the best possible. The quality of the circuits developed here is measured by circuit size, the number of circuit operations, and circuit depth, the length of the longest path between input and output vertices. Circuit size is a measure of the work necessary to execute the c...
Advances in Communication Systems, 1968
Publisher Summary This chapter discusses the progress in sequential decoding, and describes the a... more Publisher Summary This chapter discusses the progress in sequential decoding, and describes the analysis, simulation, and construction of sequential decoders. Sequential decoding procedures are important because they achieve, at modest cost, a decoding error rate that approximates that of the optimum and expensive maximum likelihood decoder. This is possible because sequential decoders allow the level of the decoding computation to fluctuate with the level of the channel noise. A sequential decoder, operated at rate less than R comp , may be constructed from a logic unit and a buffer. The logic unit can compute at several times the average computation rate, while the buffer stores data that accumulates during noisy periods. A sequential decoder is designed on the basis of the buffer overflow probability because this probability decreases slowly and as an inverse power of the product of the buffer size and machine speed. Indeed, it is stated that a sequential decoder must be designed to minimize the probability of overflow as this is generally much larger than the undetected error rate. The Wozencraft sequential decoding algorithm is a procedure for decoding tree codes or, more properly, convolutional codes (δ). Recently, a sequential decoder using the Fano algorithm was built and incorporated into a Lincoln Experimental Terminal (LET) for communication over active and passive satellite links. The decoder operates at rates ½ and ¼ bits/waveform, and the waveforms are selected by mapping groups of four binary digits at the output of the encoder into one of 16 orthogonal signals.
Optimum and suboptimum decision rules for two- channel deep space telemetry system with modulatio... more Optimum and suboptimum decision rules for two- channel deep space telemetry system with modulation consisting of PM with two orthogonal phase functions
… of Computer Science, …, 1989
Heuristics for Parallel Graph-Partitioning * t * John E. Savage Markus G. Wloka Brown University ... more Heuristics for Parallel Graph-Partitioning * t * John E. Savage Markus G. Wloka Brown University Department of Computer Science, Box 1910 Providence, Rhode Island 02912 Tel: 401-863-7600 jes@cs.brown.edu mgw@cs.brown.edu Abstract Graph partitioning is an important NP-...
The nanowire crossbar is a promising nanotechnology for assembling memories and circuits. In both... more The nanowire crossbar is a promising nanotechnology for assembling memories and circuits. In both, a small number of lithographically produced mesoscale wires (MWs) must control a large number of nanoscale wires (NWs). Previ- ous strategies for achieving this have been vunerable to mis - alignment. In this paper, we introduce core-shell NWs, whic h eliminate misalignment errors. We also give a two-step as- sembly process that reduces the amount of crossbar control circuitry.
As we saw in Chapter 1, every finite computational task can be realized by a combinational circui... more As we saw in Chapter 1, every finite computational task can be realized by a combinational circuit. While this is an important concept, it is not very practical; we cannot afford to design a special circuit for each computational task. Instead we generally perform computational tasks with machines having memory. In a strong sense to be explored in this chapter, the memory of such machines allows them to reuse their equivalent circuits to realize functions of high circuit complexity. In this chapter we examine the deterministic and nondeterministic finite-state machine (FSM), the random-access machine (RAM), and the Turing machine. The finite-state machine moves from state to state while reading input and producing output. The RAM has a central processing unit (CPU) and a random-access memory with the property that each memory word can be accessed in one unit of time. Its CPU executes instructions, reading and writing data from and to the memory. The Turing machine has a control unit...
Recent research in nanoscale computing offers multiple techniques for producing large numbers of ... more Recent research in nanoscale computing offers multiple techniques for producing large numbers of parallel nanowires (NWs). These wires can be assembled into crossbars, two orthogonal sets of parallel NWs separated by a layer of molecular devices. In a crossbar, pairs of orthogonal NWs provides control over the molecules at their crosspoints. Hysteretic molecules act as programmable diodes, allowing crossbars to function as both memories and circuits (a PLA for example). Either application requires that NWs be interfaced with existing CMOS technology.
15th Annual Symposium on Switching and Automata Theory (swat 1974), 1974
Advances in Mathematics, 1972
Internet governance is now an active topic of international discussion. Interest has been fueled ... more Internet governance is now an active topic of international discussion. Interest has been fueled by media attention to cyber crime, global surveillance, commercial espionage, cyber attacks, and threats to critical national infrastructures. Many nations have decided that they need more control over Internet-based technologies and the policies that support them. Others, emphasizing the positive aspects of these technologies, argue that traditional systems of Internet governance, which they label “multi-stakeholder” and which they associate with the success of the Internet, must continue to prevail.
Algebraic circuits combine operations drawn from an algebraic system. In this chapter we develop ... more Algebraic circuits combine operations drawn from an algebraic system. In this chapter we develop algebraic and combinatorial circuits for a variety of generally non-Boolean problems, including multiplication and inversion of matrices, convolution, the discrete Fourier transform, and sorting networks. These problems are used primarily to illustrate concepts developed in later chapters, so that this chapter may be used for reference when studying those chapters. For each of the problems examined here the natural algorithms are straight-line and the graphs are directed and acyclic; that is, they are circuits. Not only are straight-line algorithms the ones typically used for these problems, but in some cases they are the best possible. The quality of the circuits developed here is measured by circuit size, the number of circuit operations, and circuit depth, the length of the longest path between input and output vertices. Circuit size is a measure of the work necessary to execute the c...
Advances in Communication Systems, 1968
Publisher Summary This chapter discusses the progress in sequential decoding, and describes the a... more Publisher Summary This chapter discusses the progress in sequential decoding, and describes the analysis, simulation, and construction of sequential decoders. Sequential decoding procedures are important because they achieve, at modest cost, a decoding error rate that approximates that of the optimum and expensive maximum likelihood decoder. This is possible because sequential decoders allow the level of the decoding computation to fluctuate with the level of the channel noise. A sequential decoder, operated at rate less than R comp , may be constructed from a logic unit and a buffer. The logic unit can compute at several times the average computation rate, while the buffer stores data that accumulates during noisy periods. A sequential decoder is designed on the basis of the buffer overflow probability because this probability decreases slowly and as an inverse power of the product of the buffer size and machine speed. Indeed, it is stated that a sequential decoder must be designed to minimize the probability of overflow as this is generally much larger than the undetected error rate. The Wozencraft sequential decoding algorithm is a procedure for decoding tree codes or, more properly, convolutional codes (δ). Recently, a sequential decoder using the Fano algorithm was built and incorporated into a Lincoln Experimental Terminal (LET) for communication over active and passive satellite links. The decoder operates at rates ½ and ¼ bits/waveform, and the waveforms are selected by mapping groups of four binary digits at the output of the encoder into one of 16 orthogonal signals.
Optimum and suboptimum decision rules for two- channel deep space telemetry system with modulatio... more Optimum and suboptimum decision rules for two- channel deep space telemetry system with modulation consisting of PM with two orthogonal phase functions
… of Computer Science, …, 1989
Heuristics for Parallel Graph-Partitioning * t * John E. Savage Markus G. Wloka Brown University ... more Heuristics for Parallel Graph-Partitioning * t * John E. Savage Markus G. Wloka Brown University Department of Computer Science, Box 1910 Providence, Rhode Island 02912 Tel: 401-863-7600 jes@cs.brown.edu mgw@cs.brown.edu Abstract Graph partitioning is an important NP-...
The nanowire crossbar is a promising nanotechnology for assembling memories and circuits. In both... more The nanowire crossbar is a promising nanotechnology for assembling memories and circuits. In both, a small number of lithographically produced mesoscale wires (MWs) must control a large number of nanoscale wires (NWs). Previ- ous strategies for achieving this have been vunerable to mis - alignment. In this paper, we introduce core-shell NWs, whic h eliminate misalignment errors. We also give a two-step as- sembly process that reduces the amount of crossbar control circuitry.
As we saw in Chapter 1, every finite computational task can be realized by a combinational circui... more As we saw in Chapter 1, every finite computational task can be realized by a combinational circuit. While this is an important concept, it is not very practical; we cannot afford to design a special circuit for each computational task. Instead we generally perform computational tasks with machines having memory. In a strong sense to be explored in this chapter, the memory of such machines allows them to reuse their equivalent circuits to realize functions of high circuit complexity. In this chapter we examine the deterministic and nondeterministic finite-state machine (FSM), the random-access machine (RAM), and the Turing machine. The finite-state machine moves from state to state while reading input and producing output. The RAM has a central processing unit (CPU) and a random-access memory with the property that each memory word can be accessed in one unit of time. Its CPU executes instructions, reading and writing data from and to the memory. The Turing machine has a control unit...
Recent research in nanoscale computing offers multiple techniques for producing large numbers of ... more Recent research in nanoscale computing offers multiple techniques for producing large numbers of parallel nanowires (NWs). These wires can be assembled into crossbars, two orthogonal sets of parallel NWs separated by a layer of molecular devices. In a crossbar, pairs of orthogonal NWs provides control over the molecules at their crosspoints. Hysteretic molecules act as programmable diodes, allowing crossbars to function as both memories and circuits (a PLA for example). Either application requires that NWs be interfaced with existing CMOS technology.
We describe a technique for addressing individual nanoscale wires with microscale control wires w... more We describe a technique for addressing individual nanoscale wires with microscale control wires without using lithographic-scale processing to define nanoscale dimensions. Such a scheme is necessary to exploit sublithographic nanoscale storage and computational devices. Our technique uses modula- tion doping to address individual nanowires and self-assembly to organize them into nanoscale-pitch decoder arrays. We show that if coded nanowires are chosen at random from a sufficiently large population, we can ensure that a large fraction of the selected nanowires have unique addresses. For example, we show that lines can be uniquely addressesd over 99% of the time using no more than address wires. We further show a hybrid decoder scheme that only needs to address wires at a time through this sto- chastic scheme; as a result, the number of unique codes required for the nanowires does not grow with decoder size. We give an procedure to discover the addresses which are present. We also de...
We show that important local search heuristics for grid and hypercube embeddings based on the suc... more We show that important local search heuristics for grid and hypercube embeddings based on the successive swapping of pairs of vertices, such as simulated annealing, are P-hard and unlikely to run in polylogarithmic time. This puts experimental results reported in the literature into perspective: attempts to construct the exact parallel equivalent of serial simulated-annealing-based heuristics for graph embedding have yielded disappointing parallel speedups. We have developed and implemented on the Connection Machine CM-2 a new massively parallel heuristic for such embeddings, called the Mob heuristic. We report on an extensive series of experiments with our heuristics on the 32K-processor CM-2 Connection Machine for grid and hypercube embeddings that show impressive reductions in edge costs and run in less than 30 minutes on random graphs of 1 million edges. Due to excessive run times, previous heuristics reported in the literature were able to construct graph embeddings only for gr...