Mateo Valero | Barcelona Supercomputing Center (original) (raw)
Uploads
Papers by Mateo Valero
ACM Transactions on Architecture and Code Optimization, 2013
Processor architectures combining several paradigms of Thread-Level Parallelism (TLP), such as CM... more Processor architectures combining several paradigms of Thread-Level Parallelism (TLP), such as CMP processors in which each core is SMT, are becoming more and more popular as a way to improve performance at a moderate cost. However, the complex interaction between running tasks in hardware shared resources in multi-TLP architectures introduces complexities when accounting CPU time (or CPU utilization) to tasks. The CPU utilization accounted to a task depends on both the time it runs in the processor and the amount of processor hardware resources it receives. Deploying systems with accurate CPU accounting mechanisms is necessary to increase fairness. Moreover, it will allow users to be fairly charged on a shared data center, facilitating server consolidation in future systems. In this article we analyze the accuracy and hardware cost of previous CPU accounting mechanisms for pure-CMP and pure-SMT processors and we show that they are not adequate for CMP+SMT processors. Consequently, ...
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
2014 International Conference on Field-Programmable Technology (FPT), 2014
ACM SIGARCH Computer Architecture News, 2004
Modern out-of-order processors tolerate long-latency memory operations by supporting a large numb... more Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. In particular, we present some of our research having such observations as a basis to deal with future resource conscious processors.
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 2014
2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 2010
16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
Integration, the VLSI Journal, 2012
IEEE Transactions on Computers, 2005
IEEE Transactions on Computers, 1998
IEEE Transactions on Computers, 2006
ICPS '05. Proceedings. International Conference on Pervasive Services, 2005.
2008 10th IEEE International Conference on High Performance Computing and Communications, 2008
IEEE Computer Architecture Letters, 2002
ACM Transactions on Architecture and Code Optimization, 2013
Processor architectures combining several paradigms of Thread-Level Parallelism (TLP), such as CM... more Processor architectures combining several paradigms of Thread-Level Parallelism (TLP), such as CMP processors in which each core is SMT, are becoming more and more popular as a way to improve performance at a moderate cost. However, the complex interaction between running tasks in hardware shared resources in multi-TLP architectures introduces complexities when accounting CPU time (or CPU utilization) to tasks. The CPU utilization accounted to a task depends on both the time it runs in the processor and the amount of processor hardware resources it receives. Deploying systems with accurate CPU accounting mechanisms is necessary to increase fairness. Moreover, it will allow users to be fairly charged on a shared data center, facilitating server consolidation in future systems. In this article we analyze the accuracy and hardware cost of previous CPU accounting mechanisms for pure-CMP and pure-SMT processors and we show that they are not adequate for CMP+SMT processors. Consequently, ...
Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture. MICRO 29
2014 International Conference on Field-Programmable Technology (FPT), 2014
ACM SIGARCH Computer Architecture News, 2004
Modern out-of-order processors tolerate long-latency memory operations by supporting a large numb... more Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources.To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. In particular, we present some of our research having such observations as a basis to deal with future resource conscious processors.
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 2014
2010 IEEE International Symposium on Parallel & Distributed Processing (IPDPS), 2010
16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), 2007
Integration, the VLSI Journal, 2012
IEEE Transactions on Computers, 2005
IEEE Transactions on Computers, 1998
IEEE Transactions on Computers, 2006
ICPS '05. Proceedings. International Conference on Pervasive Services, 2005.
2008 10th IEEE International Conference on High Performance Computing and Communications, 2008
IEEE Computer Architecture Letters, 2002