Doran Wilde | Brigham Young University (original) (raw)
Papers by Doran Wilde
IEEE Journal on Miniaturization for Air and Space Systems
Journal of Applied Remote Sensing
2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016
Usenix, 1997
Optimizing parallel compilers need to be able to analyze nested loop programs with parametric a n... more Optimizing parallel compilers need to be able to analyze nested loop programs with parametric a ne loop bounds, in order to derive e cient parallel programs. The iteration spaces of nested loop programs can be modeled by polyhedra and systems of linear constraints. Using this model, important program analyses such as computing the number of ops executed by a loop, computing the number of memory locations or cache lines touched by a loop, and computing the amount of processor to processor communication needed during the execution of a loop| all reduce to the same mathematical problem: nding the formula for number of integer solutions to a system of parameterized linear constraints, as a function of the parameters. In this paper, we present a method for deriving a closed-form symbolic formula for the number of integer points contained in a polyhedral region in terms of size parameters. If the set of integer points to be counted lies inside a union of rational convex polytopes, then the number of points can be formulated by a special kind of polynomial called an Ehrhart pseudo-polynomial. The procedure consists of rst, computing the parametric vertices of a polytope de ned by a set of parametric linear constraints, and then solving for the pseudo-polynomial which gives the exact formula for the number of integer points in the polytope. An algorithm to derive this formula is 1 Deriving Formulae to Count Solutions to Parameterized Linear Systems 2 presented. The method is then illustrated using many examples from the literature and in the area of parallel program optimization.
Chapman & Hall/CRC Computer & Information Science Series, 2011
Practical parallel programming demands that the details of distributing data to processors and in... more Practical parallel programming demands that the details of distributing data to processors and interprocessor communication be managed by the compiler. These tasks quickly become too di cult for a programmer to do by hand for all but the simplest parallel programs. Yet, many parallel languages still require the programmer to manage much of the the parallelism. I discuss the synthesis of parallel imperative code from algorithms written in a functional language called Alpha. Alpha is based on systems of a ne recurrence equations and was designed to specify algorithms for regular array architectures. Being a functional language, Alpha implicitly supports the expression of both concurrency and communication. Thus, the programmer is freed from having to explicitly manage the parallelism. Using the information derived from static analysis, Alpha can be transformed into a form suitable for generating imperative parallel code through a series of provably correct program transformations. The kinds of analysis needed to generate e cient code for array-based functional programs are a generalization of dependency analysis, usage analysis, and scheduling techniques used in systolic array synthesis.
Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed.... more Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor Operating System designed at Brigham Young University operates in a tightly integrated system with a customized processor to improve performance and predictability. It does this by exploiting the strengths of FPGA technology in moving the majority of the kernel into
Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed.... more Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. The Small Device C Compiler (SDCC) has been retargeted to the RTP architecture and modified to produce generator directives.
Proceedings of the WESE'15: Workshop on Embedded and Cyber-Physical Systems Education - WESE'15, 2015
Journal of Aerospace Information Systems, 2014
Proceedings of the 2009 Ieee Rsj International Conference on Intelligent Robots and Systems, Oct 10, 2009
A new, simple, and fast method to compute the sharpness and curvature of a clothoid segment of a ... more A new, simple, and fast method to compute the sharpness and curvature of a clothoid segment of a continuous curvature path is presented. When generating continuous curvature paths, clothoid segments are needed to connect straight segments to perfect arc segments. This algorithm is part of a new trajectory generator and motion planner that generates smooth, natural, drivable paths, using a minimal amount of steering to reach the desired ending position similar to the way a human would drive.
Proceedings of Spie the International Society For Optical Engineering, 2005
ABSTRACT This paper describes the design of a small autonomous vehicle based on the Helios comput... more ABSTRACT This paper describes the design of a small autonomous vehicle based on the Helios computing platform, a custom FPGA-based board capable of supporting on-board vision. Target applications for the Helios computing platform are those that require lightweight equipment and low power consumption. To demonstrate the capabilities of FPGAs in real-time control of autonomous vehicles, a 16 inch long R/C monster truck was outfitted with a Helios board. The platform provided by such a small vehicle is ideal for testing and development. The proof of concept application for this autonomous vehicle was a timed race through an environment with obstacles. Given the size restrictions of the vehicle and its operating environment, the only feasible on-board sensor is a small CMOS camera. The single video feed is therefore the only source of information from the surrounding environment. The image is then segmented and processed by custom logic in the FPGA that also controls direction and speed of the vehicle based on visual input.
Programme 1 | Architectures parall eles, bases de donn ees, r eseaux et syst emes distribu es Pro... more Programme 1 | Architectures parall eles, bases de donn ees, r eseaux et syst emes distribu es Projet API Note technique n 9401 | May 1994 | 25 pages
IEEE Journal on Miniaturization for Air and Space Systems
Journal of Applied Remote Sensing
2016 26th International Conference on Field Programmable Logic and Applications (FPL), 2016
Usenix, 1997
Optimizing parallel compilers need to be able to analyze nested loop programs with parametric a n... more Optimizing parallel compilers need to be able to analyze nested loop programs with parametric a ne loop bounds, in order to derive e cient parallel programs. The iteration spaces of nested loop programs can be modeled by polyhedra and systems of linear constraints. Using this model, important program analyses such as computing the number of ops executed by a loop, computing the number of memory locations or cache lines touched by a loop, and computing the amount of processor to processor communication needed during the execution of a loop| all reduce to the same mathematical problem: nding the formula for number of integer solutions to a system of parameterized linear constraints, as a function of the parameters. In this paper, we present a method for deriving a closed-form symbolic formula for the number of integer points contained in a polyhedral region in terms of size parameters. If the set of integer points to be counted lies inside a union of rational convex polytopes, then the number of points can be formulated by a special kind of polynomial called an Ehrhart pseudo-polynomial. The procedure consists of rst, computing the parametric vertices of a polytope de ned by a set of parametric linear constraints, and then solving for the pseudo-polynomial which gives the exact formula for the number of integer points in the polytope. An algorithm to derive this formula is 1 Deriving Formulae to Count Solutions to Parameterized Linear Systems 2 presented. The method is then illustrated using many examples from the literature and in the area of parallel program optimization.
Chapman & Hall/CRC Computer & Information Science Series, 2011
Practical parallel programming demands that the details of distributing data to processors and in... more Practical parallel programming demands that the details of distributing data to processors and interprocessor communication be managed by the compiler. These tasks quickly become too di cult for a programmer to do by hand for all but the simplest parallel programs. Yet, many parallel languages still require the programmer to manage much of the the parallelism. I discuss the synthesis of parallel imperative code from algorithms written in a functional language called Alpha. Alpha is based on systems of a ne recurrence equations and was designed to specify algorithms for regular array architectures. Being a functional language, Alpha implicitly supports the expression of both concurrency and communication. Thus, the programmer is freed from having to explicitly manage the parallelism. Using the information derived from static analysis, Alpha can be transformed into a form suitable for generating imperative parallel code through a series of provably correct program transformations. The kinds of analysis needed to generate e cient code for array-based functional programs are a generalization of dependency analysis, usage analysis, and scheduling techniques used in systolic array synthesis.
Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed.... more Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor Operating System designed at Brigham Young University operates in a tightly integrated system with a customized processor to improve performance and predictability. It does this by exploiting the strengths of FPGA technology in moving the majority of the kernel into
Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed.... more Current FPGA technology has advanced to the point that useful embedded SoPCs can now be designed. The Real Time Processor (RTP) project at Brigham Young University leverages the advances in FPGA technology with a system architecture that is customizable to specific applications. The Small Device C Compiler (SDCC) has been retargeted to the RTP architecture and modified to produce generator directives.
Proceedings of the WESE'15: Workshop on Embedded and Cyber-Physical Systems Education - WESE'15, 2015
Journal of Aerospace Information Systems, 2014
Proceedings of the 2009 Ieee Rsj International Conference on Intelligent Robots and Systems, Oct 10, 2009
A new, simple, and fast method to compute the sharpness and curvature of a clothoid segment of a ... more A new, simple, and fast method to compute the sharpness and curvature of a clothoid segment of a continuous curvature path is presented. When generating continuous curvature paths, clothoid segments are needed to connect straight segments to perfect arc segments. This algorithm is part of a new trajectory generator and motion planner that generates smooth, natural, drivable paths, using a minimal amount of steering to reach the desired ending position similar to the way a human would drive.
Proceedings of Spie the International Society For Optical Engineering, 2005
ABSTRACT This paper describes the design of a small autonomous vehicle based on the Helios comput... more ABSTRACT This paper describes the design of a small autonomous vehicle based on the Helios computing platform, a custom FPGA-based board capable of supporting on-board vision. Target applications for the Helios computing platform are those that require lightweight equipment and low power consumption. To demonstrate the capabilities of FPGAs in real-time control of autonomous vehicles, a 16 inch long R/C monster truck was outfitted with a Helios board. The platform provided by such a small vehicle is ideal for testing and development. The proof of concept application for this autonomous vehicle was a timed race through an environment with obstacles. Given the size restrictions of the vehicle and its operating environment, the only feasible on-board sensor is a small CMOS camera. The single video feed is therefore the only source of information from the surrounding environment. The image is then segmented and processed by custom logic in the FPGA that also controls direction and speed of the vehicle based on visual input.
Programme 1 | Architectures parall eles, bases de donn ees, r eseaux et syst emes distribu es Pro... more Programme 1 | Architectures parall eles, bases de donn ees, r eseaux et syst emes distribu es Projet API Note technique n 9401 | May 1994 | 25 pages
This report describes the development of an operational amplifier using radiation hardened Thermi... more This report describes the development of an operational amplifier using radiation hardened Thermionic Integrated Circuits (TICs). The report is written as a tutorial to cover all aspects of the fabrication process and circuit development as well as the process and circuit modifications required to meet the integration requirements of the operational amplifier. Recent experimental results are discussed in which both devices and test circuit data are compared to theoretical computer code predictions. The development of compatible high-temperature thin-film resistors is also presented. Because the project is being terminated prior to the completion of the amplifier, suggestions are made for additional advance development.
The User's Guide for MARKAL (BNL/KFA Version 2.0) provides a user-oriented technical descript... more The User's Guide for MARKAL (BNL/KFA Version 2.0) provides a user-oriented technical description of a computer model developed for use in a multi-national energy systems-analysis study conducted jointly at Brookhaven National Laboratory (BNL) and Kernforschungsanlage Juelich (KFA). MARKAL is a flexible, multi-period, linear-programming (LP) model of a generalized energy system. It is capable of representing a wide variety of configurations