Ahmed Mohieldin | Cairo University (original) (raw)
Uploads
Papers by Ahmed Mohieldin
10th IEEE International NEWCAS Conference, 2012
ABSTRACT In this paper, an efficient ultra-low-voltage PMU working for TEG input voltages as low ... more ABSTRACT In this paper, an efficient ultra-low-voltage PMU working for TEG input voltages as low as 200mV is proposed. The PMU core, charging an energy buffer, employs a main DC/DC converter. It consists of a cascade of two Dickson-based charge pumps with a variable conversion factor and switching frequency. Feedback is provided from the load buffer by means of a current sensor to a control unit that maximizes the overall power transfer efficiency at low input voltages. System simulation results demonstrate a peak efficiency greater than 70% with a controller current consumption less than 2μA. The PMU core was simulated in Cadence environment using a UMC CMOS 180nm process and the layout of the basic core building blocks is presented. The fully-integreable design consumes an area of approximately 30mm2.
Sensors and Actuators A: Physical, 2019
In this paper, a fully-integrated reconfigurable dual-output energy harvesting system is introduc... more In this paper, a fully-integrated reconfigurable dual-output energy harvesting system is introduced. The proposed energy harvesting system provides two outputs VoutV_{out}Vout and VSC. The first output (Vout)(V_{out})(Vout) is regulated at 1.6 V and delivers the load power in the primary mode. It is generated by the primary path of the system that is implemented using a 5-stage reconfigurable boosting charge pump. In case of having more available power than the load demand, the other output (VSC)(V_{SC})(VSC) is used to charge a supercapacitor up to 3.2 V through a secondary path. The secondary path ensures both VoutV_{out}Vout regulation and maximum power point tracking of the input source to optimize end-to-end efficiency of the system. The optimization algorithm used to reconfigure the system in response to the expected variations of the input available power and the load power is also presented. The proposed system is implemented in a 0.18 mu\mumum CMOS technology and uses a total on-chip flying capacitance of...
2016 IEEE International Symposium on Antennas and Propagation (APSURSI), 2016
The architecture of a 94-GHz quasi-circulator is proposed using a hybrid coupler, directional pha... more The architecture of a 94-GHz quasi-circulator is proposed using a hybrid coupler, directional phase shifters, and a Wilkinson power divider. Different designs for the DPS are analyzed to obtain good performance. Block-level simulations are conducted to verify the operation of the proposed architecture. Good isolation between transmitter and receiver ports are demonstrated.
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs
AEU - International Journal of Electronics and Communications
IEEE Transactions on Industrial Electronics
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016
Proceedings of the 28th European Solid State Circuits Conference, Oct 24, 2002
2015 IEEE 24th International Symposium on Industrial Electronics (ISIE), 2015
Microelectronics Journal, 2015
ABSTRACT
Microelectronics Journal, 2012
A highly linear fully differential CMOS transconductor architecture based on flipped voltage foll... more A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the ...
10th IEEE International NEWCAS Conference, 2012
ABSTRACT In this paper, an efficient ultra-low-voltage PMU working for TEG input voltages as low ... more ABSTRACT In this paper, an efficient ultra-low-voltage PMU working for TEG input voltages as low as 200mV is proposed. The PMU core, charging an energy buffer, employs a main DC/DC converter. It consists of a cascade of two Dickson-based charge pumps with a variable conversion factor and switching frequency. Feedback is provided from the load buffer by means of a current sensor to a control unit that maximizes the overall power transfer efficiency at low input voltages. System simulation results demonstrate a peak efficiency greater than 70% with a controller current consumption less than 2μA. The PMU core was simulated in Cadence environment using a UMC CMOS 180nm process and the layout of the basic core building blocks is presented. The fully-integreable design consumes an area of approximately 30mm2.
Sensors and Actuators A: Physical, 2019
In this paper, a fully-integrated reconfigurable dual-output energy harvesting system is introduc... more In this paper, a fully-integrated reconfigurable dual-output energy harvesting system is introduced. The proposed energy harvesting system provides two outputs VoutV_{out}Vout and VSC. The first output (Vout)(V_{out})(Vout) is regulated at 1.6 V and delivers the load power in the primary mode. It is generated by the primary path of the system that is implemented using a 5-stage reconfigurable boosting charge pump. In case of having more available power than the load demand, the other output (VSC)(V_{SC})(VSC) is used to charge a supercapacitor up to 3.2 V through a secondary path. The secondary path ensures both VoutV_{out}Vout regulation and maximum power point tracking of the input source to optimize end-to-end efficiency of the system. The optimization algorithm used to reconfigure the system in response to the expected variations of the input available power and the load power is also presented. The proposed system is implemented in a 0.18 mu\mumum CMOS technology and uses a total on-chip flying capacitance of...
2016 IEEE International Symposium on Antennas and Propagation (APSURSI), 2016
The architecture of a 94-GHz quasi-circulator is proposed using a hybrid coupler, directional pha... more The architecture of a 94-GHz quasi-circulator is proposed using a hybrid coupler, directional phase shifters, and a Wilkinson power divider. Different designs for the DPS are analyzed to obtain good performance. Block-level simulations are conducted to verify the operation of the proposed architecture. Good isolation between transmitter and receiver ports are demonstrated.
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs
IEEE Transactions on Circuits and Systems II: Express Briefs
AEU - International Journal of Electronics and Communications
IEEE Transactions on Industrial Electronics
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
IEEE Transactions on Circuits and Systems II: Express Briefs, 2016
Proceedings of the 28th European Solid State Circuits Conference, Oct 24, 2002
2015 IEEE 24th International Symposium on Industrial Electronics (ISIE), 2015
Microelectronics Journal, 2015
ABSTRACT
Microelectronics Journal, 2012
A highly linear fully differential CMOS transconductor architecture based on flipped voltage foll... more A highly linear fully differential CMOS transconductor architecture based on flipped voltage follower (FVF) is proposed. The linearity of the proposed architecture is improved by mobility reduction compensation technique. The simulated total harmonic distortion (THD) of the ...