Amlan Chakrabarti | University of Calcutta (original) (raw)

Papers by Amlan Chakrabarti

arXiv (Cornell University), Apr 4, 2018

Nature of quantum walk in presence of multiple marked state has been studied by Nahimovs and Rivo... more Nature of quantum walk in presence of multiple marked state has been studied by Nahimovs and Rivosh [8]. They have shown that if the marked states are arranged in a √ k × √ k cluster in a √ N × √ N grid, then to find a single marked state among the multiple ones, quantum walk requires Ω( √ N -√ k) time. In this paper, we show that using lackadaisical quantum walk with the weight of the self-loop as , where k is odd, the probability of finding a marked state increases by ∼ 0.2. Furthermore, we show that instead of applying the quantum walk O(k) times to find all the marked states, classical search in the vicinity of the marked state found after the first implementation of the quantum walk can find all the marked states in O( √ k) time on average.

Quantum Information Processing

TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON)

A key challenge of the embedded era is to ensure trust in reuse of intellectual properties (IPs),... more A key challenge of the embedded era is to ensure trust in reuse of intellectual properties (IPs), which facilitates reduction of design cost and meeting of stringent marketing deadlines. Determining source of the IPs or their authenticity is a key metric to facilitate safe reuse of IPs. Though physical unclonable functions solves this problem for application specific integrated circuit (ASIC) IPs, authentication strategies for reconfigurable IPs (RIPs) or IPs of reconfigurable hardware platforms like field programmable gate arrays (FPGAs) are still in their infancy. Existing authentication techniques for RIPs that relies on verification of proof of authentication (PoA) mark embedded in the RIP by the RIP producers, leak useful clues about the PoA mark. This results in replication and implantation of the PoA mark in fake RIPs. This not only causes loss to authorized second hand RIP users, but also poses risk to the reputation of the RIP producers. We propose a zero knowledge authentication strategy for safe reusing of RIPs. The PoA of an RIP producer is kept secret and verification is carried out based on traversal times from the initial point to several intermediate points of the embedded PoA when the RIPs configure an FPGA. Such delays are user specific and cannot be replicated as these depend on intrinsic properties of the base semiconductor material of the FPGA, which is unique and never same as that of another FPGA. Experimental results validate our proposed mechanism. High strength even for low overhead ISCAS benchmarks, considered as PoA for experimentation depict the prospects of our proposed methodology.

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 2020

The present era has witnessed deployment of field programmable gate arrays (FPGAs) in cloud envir... more The present era has witnessed deployment of field programmable gate arrays (FPGAs) in cloud environments, which need to serve mixed critical tasks. For these, tasks with different criticalities need to be executed on a common platform and the property of dynamic partial reconfiguration of FPGAs make it suitable for such purposes. Several task scheduling algorithms are available which ensure suitable task schedules for such environments. However, these do not consider vulnerabilities associated with hardware. Malicious elements like hardware trojan horses (HTHs) may be present in FPGA fabric or in bitstreams procured from various third party vendors that conFigure the FPGAs. HTHs remain dormant during testing and get activated at runtime to jeopardize task executions. To ensure reliability of mixed critical tasks for FPGA based cloud environments from such vulnerabilities, we propose design of simple low overhead performance aware co-operative agents (PACA). These are associated with each FPGA and monitor their performance at runtime. On detecting an anomaly, the agent communicates with other agents of the system and outsources the tasks to ensure their secure completion. Fault diagnosis is also performed by PACA to determine whether the FPGA fabric is affected or the bitstream is affected. If the FPGA is affected, then it continues to outsource its tasks to other FPGAs, else it marks the vendor who supplied the affected bitstream as untrustworthy and avoids bitstreams procured from it in future. Thus, via multi agent cooperation, system reliability is ensured. Experimental validation is performed via the metric task success rate over normalized task deadline and increment in FPGA resources for several hardware tasks, associated with standard ISCAS and ITC 99 benchmarks. Low overhead of security components over various homogeneous FPGA environments determine the feasibility of proposed mechanism for practical applications.

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020

The present era is witnessing a reuse of hardware IPs to reduce cost. As trustworthiness is an es... more The present era is witnessing a reuse of hardware IPs to reduce cost. As trustworthiness is an essential factor, designers prefer to use hardware IPs which performed effectively in the past, but at the same time, are still active and did not age. In such scenarios, pay per use licensing schemes suit best for both producers and users. Existing pay per use licensing mechanisms consider a centralized third party, which may not be trustworthy. Hence, we seek refuge to blockchain technology to eradicate such third parties and facilitate a transparent and automated pay per use licensing mechanism. A blockchain is a distributed public ledger whose records are added based on peer review and majority consensus of its participants, that cannot be tampered or modified later. Smart contracts are deployed to facilitate the mechanism. Even dynamic pricing of the hardware IPs based on the factors of trustworthiness and aging have been focused in this work, which are not associated in existing literature. Security analysis of the proposed mechanism has been provided. Performance evaluation is carried based on the gas usage of Ethereum Solidity test environment, along with cost analysis based on lifetime and related user ratings.

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2019

Auction based scheduling strategies in current literature are essentially associated with softwar... more Auction based scheduling strategies in current literature are essentially associated with software for cloud environments, as the underlying hardware is considered generic and not re-configurable at runtime. However, recent cloud infrastructures like Amazon EC2 F1 services and Microsoft Azure deploy field programmable gate arrays (FPGAs) as an integral component, for its property of dynamic re-configuration at runtime. Auction based scheduling strategies for FPGA based cloud platforms is still not explored, where the goal is to optimize power dissipation. In this work, we try to deploy an auction based power aware scheduling mechanism for real-time task scheduling in heterogeneous FPGA based cloud platforms, which we term "Auction Based Power Aware Real-Time Scheduler" (AB-PARTS). In this mechanism, a local scheduler is invoked to execute requested tasks (periodic and non-periodic) to meet its real-time requirements. If tasks cannot be guaranteed execution in the local processing elements (PEs) or FPGAs, switch to a distributed scheduling approach with an auction scheme is made. In the auction scheme, task details are broadcasted to other schedulers, which send back an acknowledgment with reward value based on the dynamic status of the PEs of the schedulers. Task is dispatched to the scheduler, which generates the maximum reward value. The scheduler allocates the task to its PEs in such a manner so that the power consumption is optimized. For experimental purpose, we deploy a cloud platform with heterogeneous Altera FPGA boards, where performance of the proposed strategy is tested with standard tasks of the EPFL benchmark suite. Related results depict that the strategy is quite capable to achieve high resource utilization with low power consumption over different simulation scenarios.

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, 2021

2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on th... more This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement of decoupling capacitors for system on chip (SoC) design. But, early prediction and allocation of decaps at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing power, noise and delay effects for the circuit. The novelty of our work lies in exhaustive module wise estimation of di/dt drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay and noise performance to its best. We choose Double DES as example crypto-core for our test circuits as this is quite complex i...

ArXiv, 2020

As the development of Quantum computers becomes reality, the implementation of quantum algorithms... more As the development of Quantum computers becomes reality, the implementation of quantum algorithms is accelerating in a great pace. Grover's algorithm in a binary quantum system is one such quantum algorithm which solves search problems with numeric speed-ups than the conventional classical computers. Further, Grover's algorithm is extended to a ddd-ary quantum system for utilizing the advantage of larger state space. In qudit or ddd-ary quantum system n-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this paper, a generalized nnn-qudit Toffoli gate has been realized using qudits to attain a logarithmic depth decomposition without ancilla qudit. Further, the circuit for Grover's algorithm has been designed for any d-ary quantum system, where d >= 2, with the proposed nnn-qudit Toffoli gate so as to get optimized depth as compared to state-of-the-art approaches. This technique for decomposing an n-qudit Toffoli ga...

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, 2021

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, 2021

2018 21st Euromicro Conference on Digital System Design (DSD), 2018

The property of dynamic partial reconfiguration of modern field programmable gate arrays (FPGAs) ... more The property of dynamic partial reconfiguration of modern field programmable gate arrays (FPGAs) has made it feasible to execute various mixed critical tasks on the same platform. This requires partitioning the FPGA fabric into several virtual portions (VPs) and a scheduling methodology to determine which task is to be executed when and in which FPGA VP. Executing a task in an FPGA VP requires runtime configuring of the VP with a bitstream or a reconfigurable intellectual property, procured from a third party intellectual property (3PIP) vendor. Recent literature has exposed the presence of malicious elements like hardware trojan horses (HTHs) in such 3PIP bitstreams. Such HTH is particularly dangerous as these remain dormant during testing and initial stages of operation, but gets activated suddenly at runtime to jeopardize the basic security primitives of the system. Thus, reliability driven mixed critical tasks processing on FPGAs against HTH attacks is important. Firstly, reliability driven mixed critical periodic task schedule generation against HTH attacks is focused. Secondly, reliability ensured execution of mixed critical aperiodic and sporadic tasks in the generated periodic task schedule is considered. Experimentation is carried out with a variety of bitstreams and performance evaluation is performed via metrics like task success rate, task rejection rate and task preemption rate.

Communications in Computer and Information Science, 2019

Globalization of the modern semiconductor design industry has evicted the hardware root of trust.... more Globalization of the modern semiconductor design industry has evicted the hardware root of trust. Security principles are compromised at runtime due to the implantation of malicious circuitry or Hardware Trojan Horse (HTH) in the vulnerable stages of System on Chip (SoC) design, from less trusted third parties. Runtime security from integrity attacks or erroneous result generation due to HTHs is the focus of this work. The prevailing techniques adopt a redundancy based approach. Several limitations are associated with the redundancy based approach like inability to perform multitasking in a multitasking environment, inability to adapt to aging, use of fault diagnosis even in normal scenario and severe overhead in area and power. Incorporation of observe, decide and act (ODA) paradigm in the design of a SoC makes it self aware. We propose a self aware approach for facilitating runtime security, which overcomes the limitations of the existing redundancy based approach. Low overhead in area and power and better throughput than the redundancy based approaches as observed in experimental results aid its application for practical scenarios.

2020 IEEE REGION 10 CONFERENCE (TENCON), 2020

Deployment of reconfigurable hardware or field programmable gate arrays (FPGAs) in cloud platform... more Deployment of reconfigurable hardware or field programmable gate arrays (FPGAs) in cloud platforms is the modern trend. Practical scenarios include Amazon’s EC2 F1 cloud services, Microsoft’s Project Catapult and many others. Efficient task scheduling algorithms exist that can ensure green computing, i.e. order the operation of user tasks in the available FPGAs in such a manner that the power dissipated is optimum. But recent literature has exhibited eradication of the hardware root of trust, which is not taken into account by the existing task scheduling algorithms that can facilitate green computing. In this work, we analyze how vulnerability in hardware like hardware trojan horses (HTH) can increment power dissipation suddenly at runtime, without affecting the basic security primitives like integrity, confidentiality or availability of the system. Thus, are difficult to detect but may hamper the system due to unnecessary high power dissipation. We also develop a suitable runtime task scheduling algorithm which schedules the tasks at runtime based on the dynamic status of the resources, such that the power dissipation incurred at runtime is optimum. Finally, we also propose a mechanism via which we can detect affected cloud resources based on the runtime operations. We validate our proposed methodology via simulation based experiments.

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018

Scheduling in FPGAs are increasingly being employed in modern real-time embedded systems, which o... more Scheduling in FPGAs are increasingly being employed in modern real-time embedded systems, which often impose strict timeliness constraints. Deploying such a schedule requires reconfiguration at various time instants with soft IPs procured from various vendors. However, performance degradation may be associated with a compromised soft IP from an untrustworthy vendor. The present work aims at tackling such a problem with a self aware approach. The security module checks the course of the proceedings at each intermittent point of a schedule and on detecting a malicious environment, heals the scenario and takes precautions to prevent similar malfunctions in future, without hampering the pre-determined schedule. Experimental validation shows effectiveness of our proposed methodology.

The Journal of Supercomputing, 2020

The present era has witnessed deployment of reconfigurable hardware or field-programmable gate ar... more The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline-online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks. Hardware trojan horse • Real-time task scheduling • Power draining attack • FPGA * Krishnendu Guha

Microprocessors and Microsystems, 2019

ACM Transactions on Embedded Computing Systems, 2019

The semiconductor design industry of the embedded era has embraced the globalization strategy for... more The semiconductor design industry of the embedded era has embraced the globalization strategy for system on chip (SoC) design. This involves incorporation of various SoC components or intellectual properties (IPs), procured from various third-party IP (3PIP) vendors. However, trust of an SoC is challenged when a supplied IP is counterfeit or implanted with a Hardware Trojan Horse. Both roots of untrust may result in sudden performance degradation at runtime. None of the existing hardware security approaches organize the behavior of the IPs at the low level, to ensure timely completion of SoC operations. However, real-time SoC operations are always associated with a deadline, and a deadline miss due to sudden performance degradation of any of the IPs may jeopardize mission-critical applications. We seek refuge to the stigmergic behavior exhibited in insect colonies to propose a decentralized self-aware security approach. The self-aware security modules attached with each IP works bas...

ACM Journal on Emerging Technologies in Computing Systems, 2017

The rapid evolution of the embedded era has witnessed globalization for the design of SoC archite... more The rapid evolution of the embedded era has witnessed globalization for the design of SoC architectures in the semiconductor design industry. Though issues of cost and stringent marketing deadlines have been resolved in such a methodology, yet the root of hardware trust has been evicted. Malicious circuitry, a.k.a. Hardware Trojan Horse (HTH), is inserted by adversaries in the less trusted phases of design. A HTH remains dormant during testing but gets triggered at runtime to cause sudden active and passive attacks. In this work, we focus on the runtime passive threats based on the parameter delay. Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science. However, most are optimization techniques and none is dedicated to security. We seek refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threa...

arXiv (Cornell University), Apr 4, 2018

Nature of quantum walk in presence of multiple marked state has been studied by Nahimovs and Rivo... more Nature of quantum walk in presence of multiple marked state has been studied by Nahimovs and Rivosh [8]. They have shown that if the marked states are arranged in a √ k × √ k cluster in a √ N × √ N grid, then to find a single marked state among the multiple ones, quantum walk requires Ω( √ N -√ k) time. In this paper, we show that using lackadaisical quantum walk with the weight of the self-loop as , where k is odd, the probability of finding a marked state increases by ∼ 0.2. Furthermore, we show that instead of applying the quantum walk O(k) times to find all the marked states, classical search in the vicinity of the marked state found after the first implementation of the quantum walk can find all the marked states in O( √ k) time on average.

Quantum Information Processing

TENCON 2019 - 2019 IEEE Region 10 Conference (TENCON)

A key challenge of the embedded era is to ensure trust in reuse of intellectual properties (IPs),... more A key challenge of the embedded era is to ensure trust in reuse of intellectual properties (IPs), which facilitates reduction of design cost and meeting of stringent marketing deadlines. Determining source of the IPs or their authenticity is a key metric to facilitate safe reuse of IPs. Though physical unclonable functions solves this problem for application specific integrated circuit (ASIC) IPs, authentication strategies for reconfigurable IPs (RIPs) or IPs of reconfigurable hardware platforms like field programmable gate arrays (FPGAs) are still in their infancy. Existing authentication techniques for RIPs that relies on verification of proof of authentication (PoA) mark embedded in the RIP by the RIP producers, leak useful clues about the PoA mark. This results in replication and implantation of the PoA mark in fake RIPs. This not only causes loss to authorized second hand RIP users, but also poses risk to the reputation of the RIP producers. We propose a zero knowledge authentication strategy for safe reusing of RIPs. The PoA of an RIP producer is kept secret and verification is carried out based on traversal times from the initial point to several intermediate points of the embedded PoA when the RIPs configure an FPGA. Such delays are user specific and cannot be replicated as these depend on intrinsic properties of the base semiconductor material of the FPGA, which is unique and never same as that of another FPGA. Experimental results validate our proposed mechanism. High strength even for low overhead ISCAS benchmarks, considered as PoA for experimentation depict the prospects of our proposed methodology.

2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID), 2020

The present era has witnessed deployment of field programmable gate arrays (FPGAs) in cloud envir... more The present era has witnessed deployment of field programmable gate arrays (FPGAs) in cloud environments, which need to serve mixed critical tasks. For these, tasks with different criticalities need to be executed on a common platform and the property of dynamic partial reconfiguration of FPGAs make it suitable for such purposes. Several task scheduling algorithms are available which ensure suitable task schedules for such environments. However, these do not consider vulnerabilities associated with hardware. Malicious elements like hardware trojan horses (HTHs) may be present in FPGA fabric or in bitstreams procured from various third party vendors that conFigure the FPGAs. HTHs remain dormant during testing and get activated at runtime to jeopardize task executions. To ensure reliability of mixed critical tasks for FPGA based cloud environments from such vulnerabilities, we propose design of simple low overhead performance aware co-operative agents (PACA). These are associated with each FPGA and monitor their performance at runtime. On detecting an anomaly, the agent communicates with other agents of the system and outsources the tasks to ensure their secure completion. Fault diagnosis is also performed by PACA to determine whether the FPGA fabric is affected or the bitstream is affected. If the FPGA is affected, then it continues to outsource its tasks to other FPGAs, else it marks the vendor who supplied the affected bitstream as untrustworthy and avoids bitstreams procured from it in future. Thus, via multi agent cooperation, system reliability is ensured. Experimental validation is performed via the metric task success rate over normalized task deadline and increment in FPGA resources for several hardware tasks, associated with standard ISCAS and ITC 99 benchmarks. Low overhead of security components over various homogeneous FPGA environments determine the feasibility of proposed mechanism for practical applications.

2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2020

The present era is witnessing a reuse of hardware IPs to reduce cost. As trustworthiness is an es... more The present era is witnessing a reuse of hardware IPs to reduce cost. As trustworthiness is an essential factor, designers prefer to use hardware IPs which performed effectively in the past, but at the same time, are still active and did not age. In such scenarios, pay per use licensing schemes suit best for both producers and users. Existing pay per use licensing mechanisms consider a centralized third party, which may not be trustworthy. Hence, we seek refuge to blockchain technology to eradicate such third parties and facilitate a transparent and automated pay per use licensing mechanism. A blockchain is a distributed public ledger whose records are added based on peer review and majority consensus of its participants, that cannot be tampered or modified later. Smart contracts are deployed to facilitate the mechanism. Even dynamic pricing of the hardware IPs based on the factors of trustworthiness and aging have been focused in this work, which are not associated in existing literature. Security analysis of the proposed mechanism has been provided. Performance evaluation is carried based on the gas usage of Ethereum Solidity test environment, along with cost analysis based on lifetime and related user ratings.

2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), 2019

Auction based scheduling strategies in current literature are essentially associated with softwar... more Auction based scheduling strategies in current literature are essentially associated with software for cloud environments, as the underlying hardware is considered generic and not re-configurable at runtime. However, recent cloud infrastructures like Amazon EC2 F1 services and Microsoft Azure deploy field programmable gate arrays (FPGAs) as an integral component, for its property of dynamic re-configuration at runtime. Auction based scheduling strategies for FPGA based cloud platforms is still not explored, where the goal is to optimize power dissipation. In this work, we try to deploy an auction based power aware scheduling mechanism for real-time task scheduling in heterogeneous FPGA based cloud platforms, which we term "Auction Based Power Aware Real-Time Scheduler" (AB-PARTS). In this mechanism, a local scheduler is invoked to execute requested tasks (periodic and non-periodic) to meet its real-time requirements. If tasks cannot be guaranteed execution in the local processing elements (PEs) or FPGAs, switch to a distributed scheduling approach with an auction scheme is made. In the auction scheme, task details are broadcasted to other schedulers, which send back an acknowledgment with reward value based on the dynamic status of the PEs of the schedulers. Task is dispatched to the scheduler, which generates the maximum reward value. The scheduler allocates the task to its PEs in such a manner so that the power consumption is optimized. For experimental purpose, we deploy a cloud platform with heterogeneous Altera FPGA boards, where performance of the proposed strategy is tested with standard tasks of the EPFL benchmark suite. Related results depict that the strategy is quite capable to achieve high resource utilization with low power consumption over different simulation scenarios.

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, 2021

2016 20th International Symposium on VLSI Design and Test (VDAT), 2016

This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on th... more This paper addresses estimation of decoupling capacitance (decap) at sub-module stage based on their power dissipation and proper allocation of decap at the pre-layout level. Decap being in between power and ground distribution networks acts as local charge storage and effectively reduces rapid transients in the supply drop. Therefore, present trends in VLSI design are inclined towards the placement of decoupling capacitors for system on chip (SoC) design. But, early prediction and allocation of decaps at appropriate locations in the pre-layout circuit can only provide a better scope in optimizing power, noise and delay effects for the circuit. The novelty of our work lies in exhaustive module wise estimation of di/dt drop for the complete circuit, followed by an algorithmic estimation and appropriate allocation of decaps with an effort to keep power, delay and noise performance to its best. We choose Double DES as example crypto-core for our test circuits as this is quite complex i...

ArXiv, 2020

As the development of Quantum computers becomes reality, the implementation of quantum algorithms... more As the development of Quantum computers becomes reality, the implementation of quantum algorithms is accelerating in a great pace. Grover's algorithm in a binary quantum system is one such quantum algorithm which solves search problems with numeric speed-ups than the conventional classical computers. Further, Grover's algorithm is extended to a ddd-ary quantum system for utilizing the advantage of larger state space. In qudit or ddd-ary quantum system n-qudit Toffoli gate plays a significant role in the accurate implementation of Grover's algorithm. In this paper, a generalized nnn-qudit Toffoli gate has been realized using qudits to attain a logarithmic depth decomposition without ancilla qudit. Further, the circuit for Grover's algorithm has been designed for any d-ary quantum system, where d >= 2, with the proposed nnn-qudit Toffoli gate so as to get optimized depth as compared to state-of-the-art approaches. This technique for decomposing an n-qudit Toffoli ga...

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, 2021

Self Aware Security for Real Time Task Schedules in Reconfigurable Hardware Platforms, 2021

2018 21st Euromicro Conference on Digital System Design (DSD), 2018

The property of dynamic partial reconfiguration of modern field programmable gate arrays (FPGAs) ... more The property of dynamic partial reconfiguration of modern field programmable gate arrays (FPGAs) has made it feasible to execute various mixed critical tasks on the same platform. This requires partitioning the FPGA fabric into several virtual portions (VPs) and a scheduling methodology to determine which task is to be executed when and in which FPGA VP. Executing a task in an FPGA VP requires runtime configuring of the VP with a bitstream or a reconfigurable intellectual property, procured from a third party intellectual property (3PIP) vendor. Recent literature has exposed the presence of malicious elements like hardware trojan horses (HTHs) in such 3PIP bitstreams. Such HTH is particularly dangerous as these remain dormant during testing and initial stages of operation, but gets activated suddenly at runtime to jeopardize the basic security primitives of the system. Thus, reliability driven mixed critical tasks processing on FPGAs against HTH attacks is important. Firstly, reliability driven mixed critical periodic task schedule generation against HTH attacks is focused. Secondly, reliability ensured execution of mixed critical aperiodic and sporadic tasks in the generated periodic task schedule is considered. Experimentation is carried out with a variety of bitstreams and performance evaluation is performed via metrics like task success rate, task rejection rate and task preemption rate.

Communications in Computer and Information Science, 2019

Globalization of the modern semiconductor design industry has evicted the hardware root of trust.... more Globalization of the modern semiconductor design industry has evicted the hardware root of trust. Security principles are compromised at runtime due to the implantation of malicious circuitry or Hardware Trojan Horse (HTH) in the vulnerable stages of System on Chip (SoC) design, from less trusted third parties. Runtime security from integrity attacks or erroneous result generation due to HTHs is the focus of this work. The prevailing techniques adopt a redundancy based approach. Several limitations are associated with the redundancy based approach like inability to perform multitasking in a multitasking environment, inability to adapt to aging, use of fault diagnosis even in normal scenario and severe overhead in area and power. Incorporation of observe, decide and act (ODA) paradigm in the design of a SoC makes it self aware. We propose a self aware approach for facilitating runtime security, which overcomes the limitations of the existing redundancy based approach. Low overhead in area and power and better throughput than the redundancy based approaches as observed in experimental results aid its application for practical scenarios.

2020 IEEE REGION 10 CONFERENCE (TENCON), 2020

Deployment of reconfigurable hardware or field programmable gate arrays (FPGAs) in cloud platform... more Deployment of reconfigurable hardware or field programmable gate arrays (FPGAs) in cloud platforms is the modern trend. Practical scenarios include Amazon’s EC2 F1 cloud services, Microsoft’s Project Catapult and many others. Efficient task scheduling algorithms exist that can ensure green computing, i.e. order the operation of user tasks in the available FPGAs in such a manner that the power dissipated is optimum. But recent literature has exhibited eradication of the hardware root of trust, which is not taken into account by the existing task scheduling algorithms that can facilitate green computing. In this work, we analyze how vulnerability in hardware like hardware trojan horses (HTH) can increment power dissipation suddenly at runtime, without affecting the basic security primitives like integrity, confidentiality or availability of the system. Thus, are difficult to detect but may hamper the system due to unnecessary high power dissipation. We also develop a suitable runtime task scheduling algorithm which schedules the tasks at runtime based on the dynamic status of the resources, such that the power dissipation incurred at runtime is optimum. Finally, we also propose a mechanism via which we can detect affected cloud resources based on the runtime operations. We validate our proposed methodology via simulation based experiments.

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 2018

Scheduling in FPGAs are increasingly being employed in modern real-time embedded systems, which o... more Scheduling in FPGAs are increasingly being employed in modern real-time embedded systems, which often impose strict timeliness constraints. Deploying such a schedule requires reconfiguration at various time instants with soft IPs procured from various vendors. However, performance degradation may be associated with a compromised soft IP from an untrustworthy vendor. The present work aims at tackling such a problem with a self aware approach. The security module checks the course of the proceedings at each intermittent point of a schedule and on detecting a malicious environment, heals the scenario and takes precautions to prevent similar malfunctions in future, without hampering the pre-determined schedule. Experimental validation shows effectiveness of our proposed methodology.

The Journal of Supercomputing, 2020

The present era has witnessed deployment of reconfigurable hardware or field-programmable gate ar... more The present era has witnessed deployment of reconfigurable hardware or field-programmable gate arrays (FPGAs) in diverse domains like automation and avionics, which are cyber physical in nature. Such cyber physical systems are associated with strict power budgets. Efficient real-time task-scheduling strategies exist that ensure execution of maximum number of tasks within the power budget. However, these do not consider hardware threats into account. Recent literature has exposed the existence of hardware trojan horses (HTHs). HTHs are malicious circuitry that remain dormant during testing and evade detection, but get activated at runtime to jeopardize operations. HTHs can be etched into the FPGA fabric by adversaries in the untrustworthy foundries, during fabrication of the FPGAs. Even vendors selling reconfigurable intellectual properties or bitstreams that configure the FPGA fabric for task operation may insert HTHs during writing the bitstream codes. HTHs may cause a variety of attacks which may affect the basic security primitives of the system like its integrity, confidentiality or availability. In this work, we explore how power draining ability of HTHs may reduce lifetime of the system. A self-aware approach is also proposed which detects the affected resources of the system and eradicates their use in future to facilitate system reliability. An offline-online scheduling strategy is proposed for periodic tasks which can ensure reliability of their operations till the expected lifetime of the system. Accommodating non-periodic tasks in the periodic task schedule based on available power is also focused. For experimentation, we consider tasks associated with EPFL benchmarks and demonstrate results based on the metric task success rate for periodic tasks and metric task rejection rate for non-periodic tasks. Hardware trojan horse • Real-time task scheduling • Power draining attack • FPGA * Krishnendu Guha

Microprocessors and Microsystems, 2019

ACM Transactions on Embedded Computing Systems, 2019

The semiconductor design industry of the embedded era has embraced the globalization strategy for... more The semiconductor design industry of the embedded era has embraced the globalization strategy for system on chip (SoC) design. This involves incorporation of various SoC components or intellectual properties (IPs), procured from various third-party IP (3PIP) vendors. However, trust of an SoC is challenged when a supplied IP is counterfeit or implanted with a Hardware Trojan Horse. Both roots of untrust may result in sudden performance degradation at runtime. None of the existing hardware security approaches organize the behavior of the IPs at the low level, to ensure timely completion of SoC operations. However, real-time SoC operations are always associated with a deadline, and a deadline miss due to sudden performance degradation of any of the IPs may jeopardize mission-critical applications. We seek refuge to the stigmergic behavior exhibited in insect colonies to propose a decentralized self-aware security approach. The self-aware security modules attached with each IP works bas...

ACM Journal on Emerging Technologies in Computing Systems, 2017

The rapid evolution of the embedded era has witnessed globalization for the design of SoC archite... more The rapid evolution of the embedded era has witnessed globalization for the design of SoC architectures in the semiconductor design industry. Though issues of cost and stringent marketing deadlines have been resolved in such a methodology, yet the root of hardware trust has been evicted. Malicious circuitry, a.k.a. Hardware Trojan Horse (HTH), is inserted by adversaries in the less trusted phases of design. A HTH remains dormant during testing but gets triggered at runtime to cause sudden active and passive attacks. In this work, we focus on the runtime passive threats based on the parameter delay. Nature-inspired algorithms offer an alternative to the conventional techniques for solving complex problems in the domain of computer science. However, most are optimization techniques and none is dedicated to security. We seek refuge to the crypsis behavior exhibited by geckos in nature to generate a runtime security technique for SoC architectures, which can bypass runtime passive threa...