Routing and Patterning Simplification with a Diagonal Via Grid (original) (raw)
Yesterday, I posted a YouTube video on simplifying multipatterning for the 2nm-class logic node (48 nm gate/M1 pitch, 28 nm routing track pitch). Here is the recap.
The key enabler of this simplification is the use of a via grid formed by intersecting diagonal lines, as described in TSMC’s patent US9530727 (Figure 1).
Figure 1. Via placement on a grid of intersecting diagonal lines (US Patent 9530727).
This constrains line cut locations to follow local diagonal line grids. Along the same line, the minimum distance for two via landings must fit between cuts. These constraints make DUV multipatterning easier, by reducing the number of required masks. A fully self-aligned V1 layer can be patterned with LELE (Figure 2), since the via dimensions are already defined by the underlying and overlying metal widths.
Figure 2. Patterning of a fully self-aligned V1 layer by DUV LELE.
The M1 and M2 layers can be patterned by SADP+LELE cut and SADP-cut-SADP-block, respectively, as mentioned in my previous article on SiCarrier’s patent.
You can get the full details in the video here: 2nm Routing and Patterning Simplification with Diagonal Via Grid