Ariel Pola | Universidad Nacional de Córdoba (original) (raw)

Papers by Ariel Pola

2020 IEEE Photonics Conference (IPC)

We investigate a reduced complexity adaptive equalizer for compensating the transmitter I/Q time ... more We investigate a reduced complexity adaptive equalizer for compensating the transmitter I/Q time skew and the phase and gain errors of the optical modulator, in sub-carrier multiplexing (SCM) receivers. The performance is evaluated by using an FPGA-platform based implementation.

IEEE Transactions on Circuits and Systems I: Regular Papers

2016 8th IEEE Latin-American Conference on Communications (LATINCOM), 2016

Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) a... more Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for optimization and performance evaluation of LDPC codes. The proposed FPGA framework includes several features such as the capability of changing the internal resolution of the decoder algorithm or capturing error patterns for error-floor analysis. Experimental results derived from the FPGA platform show that the designed QC-LDPC code is able to achieve an NCG of 11.6 dB at a bit-error-rate (BER) of 10−15 with an overhead of 25% and a codeword length of only 16K bits.

As a result of the steady increase in data traffic, the telecommunications industry has evolved d... more As a result of the steady increase in data traffic, the telecommunications industry has evolved dramatically in recent years. In this context, new digital communications transceivers that outperform processing speed are required. This speed increase combined with the limitations of the bandwidth communications channel exacerbate the impacts of the intersymbol interference (ISI). In order to compensate for this effect, it is necessary to implement efficient receiver equalization schemes. The decision feedback equalizer (DFE) is one of the most popular equalization techniques in industry, featuring a good relationship between performance and complexity. Unfortunately, its use in high speed systems has been limited due to the high complexity reached when processing techniques are used in parallel as a result of the existence of feedback loops. In particular, the complexity of the existing techniques increases exponentially with the channel memory, leading to a restriction in the use of...

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016

Journal of Electrical and Computer Engineering, 2013

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in... more This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

This paper introduces the decision feedforward equalizer (DFFE), a new low complexity iterative e... more This paper introduces the decision feedforward equalizer (DFFE), a new low complexity iterative equalization architecture for high speed receivers used on channels with large intersymbol interference (ISI). The decision feedback equalizer (DFE) is one of the preferred receivers for high ISI channels. The high data and symbol rate of current communications systems often require parallel processing receiver implementations [1]. Unfortunately, the complexity of parallel architectures of the DFE grows exponentially with the channel memory [2] and limits their application to low ISI channels. The DFFE avoids the exponential growth of the DFE by using tentative decisions to iteratively cancel the ISI. We show that the DFFE can achieve performance similar to the DFE. These benefits make it an excellent choice for high-speed receivers required to operate over highly dispersive channels.

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers op... more This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers operating on highly dispersive channels. The DFFE has been recently proposed for multigigabit communication receivers, where the use of parallel processing is required. Well-known parallel architectures for the traditional decision feedback equalizer (DFE) have a complexity which grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to iteratively cancel intersymbol interference (ISI). Additional complexity reduction can be achieved by improving the reliability of the initial tentative decisions. To provide more reliable initial tentative decisions to the DFFE, a simple reduced-state Viterbi algorithm (VA) is proposed in this work. Computer simulations demonstrate that the combination of DFFE and VA not only allows a similar performance to the typical DFE to be achieved, but it also results in a significant complexity reduction.

2020 IEEE Photonics Conference (IPC)

We investigate a reduced complexity adaptive equalizer for compensating the transmitter I/Q time ... more We investigate a reduced complexity adaptive equalizer for compensating the transmitter I/Q time skew and the phase and gain errors of the optical modulator, in sub-carrier multiplexing (SCM) receivers. The performance is evaluated by using an FPGA-platform based implementation.

IEEE Transactions on Circuits and Systems I: Regular Papers

2016 8th IEEE Latin-American Conference on Communications (LATINCOM), 2016

Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) a... more Powerful forward error correction codes such as quasi-cyclic low density parity check (QC-LDPC) are required in next-generation coherent optical communication systems [1]. This work describes the design and experimental verification of a high net coding gain (NCG), low complexity QC-LDPC code. Towards this end, we develop a field programmable gate array (FPGA) based platform specially designed for optimization and performance evaluation of LDPC codes. The proposed FPGA framework includes several features such as the capability of changing the internal resolution of the decoder algorithm or capturing error patterns for error-floor analysis. Experimental results derived from the FPGA platform show that the designed QC-LDPC code is able to achieve an NCG of 11.6 dB at a bit-error-rate (BER) of 10−15 with an overhead of 25% and a codeword length of only 16K bits.

As a result of the steady increase in data traffic, the telecommunications industry has evolved d... more As a result of the steady increase in data traffic, the telecommunications industry has evolved dramatically in recent years. In this context, new digital communications transceivers that outperform processing speed are required. This speed increase combined with the limitations of the bandwidth communications channel exacerbate the impacts of the intersymbol interference (ISI). In order to compensate for this effect, it is necessary to implement efficient receiver equalization schemes. The decision feedback equalizer (DFE) is one of the most popular equalization techniques in industry, featuring a good relationship between performance and complexity. Unfortunately, its use in high speed systems has been limited due to the high complexity reached when processing techniques are used in parallel as a result of the existence of feedback loops. In particular, the complexity of the existing techniques increases exponentially with the channel memory, leading to a restriction in the use of...

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS), 2016

Journal of Electrical and Computer Engineering, 2013

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in... more This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2011

This paper introduces the decision feedforward equalizer (DFFE), a new low complexity iterative e... more This paper introduces the decision feedforward equalizer (DFFE), a new low complexity iterative equalization architecture for high speed receivers used on channels with large intersymbol interference (ISI). The decision feedback equalizer (DFE) is one of the preferred receivers for high ISI channels. The high data and symbol rate of current communications systems often require parallel processing receiver implementations [1]. Unfortunately, the complexity of parallel architectures of the DFE grows exponentially with the channel memory [2] and limits their application to low ISI channels. The DFFE avoids the exponential growth of the DFE by using tentative decisions to iteratively cancel the ISI. We show that the DFFE can achieve performance similar to the DFE. These benefits make it an excellent choice for high-speed receivers required to operate over highly dispersive channels.

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers op... more This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers operating on highly dispersive channels. The DFFE has been recently proposed for multigigabit communication receivers, where the use of parallel processing is required. Well-known parallel architectures for the traditional decision feedback equalizer (DFE) have a complexity which grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to iteratively cancel intersymbol interference (ISI). Additional complexity reduction can be achieved by improving the reliability of the initial tentative decisions. To provide more reliable initial tentative decisions to the DFFE, a simple reduced-state Viterbi algorithm (VA) is proposed in this work. Computer simulations demonstrate that the combination of DFFE and VA not only allows a similar performance to the typical DFE to be achieved, but it also results in a significant complexity reduction.