Application-Specific Systems, Architectures, and Processors 2014 (original) (raw)

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ASAP 2014: Zurich, Switzerland

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  • Session 1: Hardware Accelerators I
  • Session 2: Computer Arithmetic
  • Poster Session I
  • Session 3: Performance and Power Analysis
  • Session 4: Architectures I
  • Session5: Programming Regular Papers
  • Poster Session 2
  • Session 6: Hardware Accelerators II
  • Session7: Memory Regular Papers
  • Session 8: Architectures II

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  IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2014, Zurich, Switzerland, June 18-20, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-3609-0

Session 1: Hardware Accelerators I

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  Kubilay Atasu:
  Resource-efficient regular expression matching architecture for text analytics. 1-8
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  Yuk-Ming Choi, Hayden Kwok-Hay So:
  Map-reduce processing of k-means algorithm with FPGA-accelerated computer cluster. 9-16
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  Iñaki Bildosola, Unai Martinez-Corral, Koldo Basterretxea:
  Adaptive scalable SVD unit for fast processing of large LSE problems. 17-24
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  Michael Gautschi, Michael Muehlberghuber, Andreas Traber, Sven Stucki, Matthias Baer, Renzo Andri, Luca Benini, Beat Muheim, Hubert Kaeslin:
  SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC. 25-29
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  Mohammad Badawi, Ahmed Hemani, Zhonghai Lu:
  Customizable coarse-grained energy-efficient reconfigurable packet processing architecture. 30-35
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  Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker, Wayne Luk:
  Low latency FPGA acceleration of market data feed arbitration. 36-40

Session 2: Computer Arithmetic

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  Florent de Dinechin, Matei Istoan, Abdelbassat Massouri:
  Sum-of-product architectures computing just right. 41-47
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  Hamad Alrimeih, Daler N. Rakhmatov:
  Pipelined modular multiplier supporting multiple standard prime fields. 48-56
• 
  Karim Bigou, Arnaud Tisserand:
  RNS modular multiplication through reduced base extensions. 57-62
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  Mioara Joldes, Jean-Michel Muller, Valentina Popescu:
  On the computation of the reciprocal of floating point expansions using an adapted Newton-Raphson iteration. 63-67

Poster Session I

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  Amro Altamimi, Daler N. Rakhmatov, Michael McGuire:
  Polar baseband receiver for low-end WLAN. 68-69
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  Yun-Nan Chang, Ting-Chi Tong:
  Design of a 2D graphics front-end rendering processor. 70-71
• 
  Michael J. Hall, Roger D. Chamberlain:
  Performance modeling of virtualized custom logic computations. 72-73
• 
  Ali Hayek, Bashier Machmur, Michael Schreiber, Josef Börcsök, Stefan Golz, Mario Epp:
  HICore1: "Safety on a chip" turnkey solution for industrial control. 74-75
• 
  Mehdi Modarressi, Hamid Sarbazi-Azad:
  A reconfigurable network-on-chip architecture for heterogeneous CMPs in the dark-silicon era. 76-77
• 
  Simon Pontie, Paolo Maistri:
  Randomized windows for secure scalar multiplication on elliptic curves. 78-79
• 
  Mariagiovanna Sami, Gianluca Palermo:
  Virtual semi-concurrent self-checking for heterogeneous MPSoC architectures. 80-81
• 
  Hao Xiao, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Guanyu Zhu:
  Distributed synchronization for message-passing based embedded multiprocessors. 82-83

Session 3: Performance and Power Analysis

• 
  Lin Ma, Roger D. Chamberlain, Kunal Agrawal:
  Performance modeling for highly-threaded many-core GPUs. 84-91
• 
  Heiner Giefers, Raphael Polig, Christoph Hagleitner:
  Analyzing the energy-efficiency of dense linear algebra kernels by power-profiling a hybrid CPU/FPGA system. 92-99
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  Nathaniel A. Conos, Saro Meguerdichian, Miodrag Potkonjak:
  Coordinated and adaptive power gating and dynamic voltage scaling for energy minimization. 100-107
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  Ahmad Lashgar, Amirali Baniasadi:
  A case against small data types in GPGPUs. 108-113

Session 4: Architectures I

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  Francesco Conti, Chuck Pilkington, Andrea Marongiu, Luca Benini:
  He-P2012: Architectural heterogeneity exploration on a scalable many-core platform. 114-120
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  Hamed Tabkhi, Robert Bushey, Gunar Schirner:
  Function-Level Processor (FLP): Raising efficiency by operating at function granularity for market-oriented MPSoC. 121-130
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  Waqar Hussain, Roberto Airoldi, Henry Hoffmann, Tapani Ahonen, Jari Nurmi:
  Design of an accelerator-rich architecture by integrating multiple heterogeneous coarse grain reconfigurable arrays over a network-on-chip. 131-138
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  Ruan de Clercq, Frank Piessens, Dries Schellekens, Ingrid Verbauwhede:
  Secure interrupts on low-end microcontrollers. 147-152

Session5: Programming Regular Papers

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  Konstantinos Krommydas, Wu-chun Feng, Muhsen Owaida, Christos D. Antonopoulos, Nikolaos Bellas:
  On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms. 153-160
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  Edoardo Paone, Davide Gadioli, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano:
  Evaluating orthogonality between application auto-tuning and run-time resource management for adaptive OpenCL applications. 161-168
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  Thomas Peyret, Gwenolé Corre, Mathieu Thevenin, Kevin J. M. Martin, Philippe Coussy:
  Efficient application mapping on CGRAs based on backward simultaneous scheduling/binding and dynamic graph transformations. 169-172
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  Moritz Schmid, Alexandru Tanase, Frank Hannig, Jürgen Teich, Vivek Singh Bhadouria, Dibyendu Ghoshal:
  Domain-specific augmentations for High-Level Synthesis. 173-177

Poster Session 2

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  Junyi Han, Robert Haines, Adel Salhli, John Martin Brooke, Bruce D'Amora, Bob Danani:
  Virtual science on the move: Interactive access to simulations on supercomputers. 178-179
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  Keerthan Jaic, Melissa C. Smith, Nilim Sarma:
  A practical network intrusion detection system for inline FPGAs on 10GbE network adapters. 180-181
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  Yanhua Li, Youhui Zhang, Jianfeng Yang, Wayne Luk, Guangwen Yang, Weimin Zheng:
  An approach of processor core customization for stencil computation. 182-183
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  Yongchao Liu, Bertil Schmidt:
  SWAPHI: Smith-waterman protein database search on Xeon Phi coprocessors. 184-185
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  Kevin Shen-Hoong Ong, Suhaib A. Fahmy, Keck Voon Ling:
  A scalable and compact systolic architecture for linear solvers. 186-187
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  Zoltán Endre Rákossy, Farhad Merchant, Axel Acosta-Aponte, S. K. Nandy, Anupam Chattopadhyay:
  Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. 188-189
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  Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto:
  Bandwidth compression of multiple numerical data streams for high performance custom computing. 190-191
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  Shizhen Xu, Xiaomeng Huang, Yan Zhang, Yong Hu, Guangwen Yang:
  A customized GPU acceleration of the princeton ocean model. 192-193

Session 6: Hardware Accelerators II

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  Ce Guo, Wayne Luk, Stephen Weston:
  Pipelined reconfigurable accelerator for ordinal pattern encoding. 194-201
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  Janarbek Matai, Joo-Young Kim, Ryan Kastner:
  Energy efficient canonical huffman encoding. 202-209
• 
  Zhenzhi Wu, Dake Liu:
  Flexible multistandard FEC processor design with ASIP methodology. 210-218
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  Kevin Cushon, Saied Hemati, Shie Mannor, Warren J. Gross:
  Energy-efficient gear-shift LDPC decoders. 219-223

Session7: Memory Regular Papers

• 
  Christian Pinto, Luca Benini:
  Exploring DMA-assisted prefetching strategies for software caches on multicore clusters. 224-231
• 
  Majid Jalili, Hamid Sarbazi-Azad:
  A compression-based morphable PCM architecture for improving resistance drift tolerance. 232-239

Session 8: Architectures II

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  Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero:
  PVMC: Programmable Vector Memory Controller. 240-247
• 
  Berkin Akin, Franz Franchetti, James C. Hoe:
  Understanding the design space of DRAM-optimized hardware FFT accelerators. 248-255
• 
  Deepak Gangadharan, Jürgen Teich, Samarjit Chakraborty:
  Quality-aware video decoding on thermally-constrained MPSoC platforms. 256-263
• 
  João Andrade, Frederico Pratas, Gabriel Falcão, Vítor Manuel Mendes da Silva, Leonel Sousa:
  Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era. 264-269

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