Design, Automation, and Test in Europe 2010 (original) (raw)

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  • Keynote Addresses
  • Green and Emerging Technologies for Low Power
  • Variability Aware Low Power Design
  • Power Optimization and Estimation for Flash and CMOS Technologies
  • Addressing the Challenge of Technology Scaling
  • Statistical Validation at 45nm and Beyond
  • Cool Computing Platforms (Cool Electronic Systems Day)
  • Multi-Level, Multi-Domain System Simulation
  • Characterizing and Optimizing NoC Performance
  • Industrially-Oriented Formal Verification
  • Hot Topic - 3D Stacked ICs: Technology, Design and Test

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• 
  Giovanni De Micheli, Bashir M. Al-Hashimi, Wolfgang Müller, Enrico Macii:
  Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-7054-9

Keynote Addresses

• 
  Alberto L. Sangiovanni-Vincentelli:
  All things are connected. 1
• 
  Hermann Eul:
  Wireless communication - successful differentiation on standard technology by innovation. 2

Embedded Tutorial - Embedded Systems and their Physical Environment - The 'Cyberphysical' View

• 
  Albert Benveniste:
  Loosely Time-Triggered Architectures for Cyber-Physical Systems. 3-8

Power-Aware Technique for Real-Time Systems

• 
  Chuan-Yue Yang, Jian-Jia Chen, Lothar Thiele, Tei-Wei Kuo:
  Energy-efficient real-time task scheduling with temperature-dependent leakage. 9-14
• 
  Sandro Penolazzi, Ingo Sander, Ahmed Hemani:
  Predicting energy and performance overhead of Real-Time Operating Systems. 15-20
• 
  Min Bao, Alexandru Andrei, Petru Eles, Zebo Peng:
  Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling. 21-26

System Level Design of Multicores

• 
  Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier:
  Multicore soft error rate stabilization using adaptive dual modular redundancy. 27-32
• 
  Yvain Thonnart, Pascal Vivet, Fabien Clermidy:
  A fully-asynchronous low-power framework for GALS NoC integration. 33-38
• 
  Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen:
  Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. 39-44
• 
  Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Rostagno, Maurizio Zamboni:
  MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture. 45-50

Reliability, Simulation, Yield and Enhancement

• 
  Lin Huang, Qiang Xu:
  AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs. 51-56
• 
  Paul Zuber, Miguel Miranda, Petr Dobrovolný, Koen van der Zanden, Jong-Hoon Jung:
  Statistical SRAM analysis for yield enhancement. 57-62
• 
  Mingjing Chen, Alex Orailoglu:
  Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme. 63-68
• 
  Sheng Yang, Bashir M. Al-Hashimi, David Flynn, S. Saqib Khursheed:
  Scan based methodology for reliable state retention power gating designs. 69-74

Advances in Embedded Software Development

• 
  Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten:
  TLM+ modeling of embedded HW/SW systems. 75-80
• 
  Matthias Traub, Thilo Streichert, Oleg Krasovytskyy, Jürgen Becker:
  Scenario extraction for a refined timing-analysis of automotive network topologies. 81-86
• 
  Kebin Zeng, Yu Guo, Christo Angelov:
  Graphical Model Debugger Framework for embedded systems. 87-92
• 
  Shuai Mu, Xinya Zhang, Nairen Zhang, Jiaxin Lu, Yangdong Steve Deng, Shu Zhang:
  IP routing processing with graphic processors. 93-98

Memory Stacking and Cooling Solutions

• 
  Igor Loi, Luca Benini:
  An efficient distributed memory interface for many-core platform with 3D stacked DRAM. 99-104
• 
  Andrea Marongiu, Martino Ruggiero, Luca Benini:
  Efficient OpenMP data mapping for multicore platforms with vertically stacked memory. 105-110
• 
  Ayse K. Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler, Bruno Michel:
  Energy-efficient variable-flow liquid cooling in 3D stacked architectures. 111-116
• 
  Jieyi Long, Seda Ogrenci Memik, Matthew Grayson:
  Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers. 117-122

Panel

• 
  Bryon Moyer, Joachim Kunkel, John Cornish, Chris Rowen, Eshel Haritan, Yankin Tanurhan:
  Are we there yet? Has IP block assembly become as easy as LEGO? 123

Green and Emerging Technologies for Low Power

• 
  Ehsan Pakbaznia, Mohammad Ghasemazar, Massoud Pedram:
  Temperature-aware dynamic resource provisioning in a power-optimized datacenter. 124-129
• 
  Michael B. Henry, Leyla Nazhandali:
  From transistors to MEMS: Throughput-aware power gating in CMOS circuits. 130-135
• 
  Yongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie:
  Energy- and endurance-aware design of phase change memory caches. 136-141
• 
  Mustafa Imran Ali, Bashir M. Al-Hashimi, Joaquín Recas, David Atienza:
  Evaluation and design exploration of solar harvested-energy prediction algorithm. 142-147

Game-Changing Technologies for System Des

• 
  Yiran Chen, Hai Li, Xiaobin Wang, Wenzhong Zhu, Wei Xu, Tong Zhang:
  A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). 148-153
• 
  Tsung-Ching Huang, Kenjiro Fukuda, Chun-Ming Lo, Yung-Hui Yeh, Tsuyoshi Sekitani, Takao Someya, Kwang-Ting Cheng:
  Pseudo-CMOS: A novel design style for flexible electronics. 154-159
• 
  Héctor J. García, Igor L. Markov:
  Spinto: High-performance energy minimization in spin glasses. 160-165
• 
  Ang-Chih Hsieh, TingTing Hwang, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
  TSV redundancy: Architecture and design issues in 3D IC. 166-171

Application Development for Multicores

• 
  Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan:
  A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. 172-177
• 
  R. Grottesi, Serena Morigi, Martino Ruggiero, Luca Benini:
  Parallel subdivision surface rendering and animation on the Cell BE processor. 178-183
• 
  Camille Jalier, Didier Lattard, Ahmed Amine Jerraya, Gilles Sassatelli, Pascal Benoit, Lionel Torres:
  Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem. 184-189
• 
  Rebecca L. Collins, Bharadwaj Vellore, Luca P. Carloni:
  Recursion-driven parallel code generation for multi-core platforms. 190-195
• 
  Giovanni Mariani, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
  An industrial design space exploration framework for supporting run-time resource management on multi-core systems. 196-201

Advanced System Chip Testing

• 
  A. M. Majid, David C. Keezer:
  Stretching the limits of FPGA SerDes for enhanced ATE performance. 202-207
• 
  Zhiyuan He, Zebo Peng, Petru Eles:
  Multi-temperature testing for core-based system-on-chip. 208-213
• 
  Ad J. van de Goor, Georgi Gaydadjiev, Said Hamdioui:
  Memory testing with a RISC microcontroller. 214-219

Real-Time Scheduling in Embedded Systems

• 
  Alejandro Masrur, Samarjit Chakraborty, Georg Färber:
  Constant-time admission control for Deadline Monotonic tasks. 220-225
• 
  Jonas Rox, Rolf Ernst:
  Exploiting inter-event stream correlations between output event streams of non-preemptively scheduled tasks. 226-231
• 
  Hessam Kooti, Elaheh Bozorgzadeh, Shenghui Liao, Lichun Bao:
  Transition-aware real-time task scheduling for reconfigurable embedded systems. 232-237

Architectural Techniques for Robust Design

• 
  Songjun Pan, Yu Hu, Xiaowei Li:
  IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults. 238-243
• 
  Hamed F. Dadgour, Kaustav Banerjee:
  Aging-resilient design of pipelined architectures using novel detection and correction circuits. 244-249
• 
  Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz:
  An integrated framework for joint design space exploration of microarchitecture and circuits. 250-255

HOT TOPIC - AUTOSAR and Automotive Software Design

• 
  Simon Fürst:
  Challenges in the design of automotive software. 256-258
• 
  Stefan Voget:
  AUTOSAR and the automotive tool chain. 259-262
• 
  Dirk Diekhoff:
  AUTOSAR basic software for complex control units. 263-266

Interactive Presentations

• 
  Jing Cao, Albert Nymeyer:
  High-fidelity markovian power model for protocols. 267-270
• 
  Arpad Gellert, Gianluca Palermo, Vittorio Zaccaria, Adrian Florea, Lucian N. Vintan, Cristina Silvano:
  Energy-performance design space exploration in SMT architectures exploiting selective load value predictions. 271-274
• 
  Vladimir Pasca, Lorena Anghel, Claudia Rusu, Riccardo Locatelli, Massimo Coppola:
  Error resilience of intra-die and inter-die communication with 3D spidergon STNoC. 275-278
• 
  Muhammad Bashir, Linda S. Milor:
  Towards a chip level reliability simulator for copper/low-k backend processes. 279-282
• 
  Seyab, Said Hamdioui:
  NBTI modeling in the framework of temperature variation. 283-286
• 
  Chi-Neng Wen, Shu-Hsuan Chou, Tien-Fu Chen, Tay-Jyi Lin:
  RunAssert: A non-intrusive run-time assertion for parallel programs debugging. 287-290
• 
  Marco Facchini, Paul Marchal, Francky Catthoor, Wim Dehaene:
  An RDL-configurable 3D memory tier to replace on-chip SRAM. 291-294
• 
  Raid Zuhair Ayoub, Shervin Sharifi, Tajana Simunic Rosing:
  GentleCool: Cooling aware proactive workload scheduling in multi-machine systems. 295-298
• 
  Niklas Lotze, Jacob Göppert, Yiannos Manoli:
  Timing modeling for digital sub-threshold circuits. 299-302
• 
  M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
  Power consumption of logic circuits in ambipolar carbon nanotube technology. 303-306
• 
  Min Li, Yexin Zheng, Michael S. Hsiao, Chao Huang:
  Reversible logic synthesis through ant colony optimization. 307-310
• 
  Prateek Mishra, Niraj K. Jha:
  Low-power FinFET circuit synthesis using surface orientation optimization. 311-314
• 
  Kalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish:
  Implementing digital logic with sinusoidal supplies. 315-318
• 
  Antonino Tumeo, Francesco Regazzoni, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
  A reconfigurable multiprocessor architecture for a reliable face recognition implementation. 319-322
• 
  Alexander Krupp, Wolfgang Müller:
  A systematic approach to the test of combined HW/SW systems. 323-326
• 
  Steffen Ostendorff, Heinz-Dietrich Wuttke, Jörg Sachße, S. Köhler:
  A new approach for adaptive failure diagnostics based on emulation test. 327-330
• 
  Karthik Lakshmanan, Gaurav Bhatia, Ragunathan Rajkumar:
  Integrated end-to-end timing analysis of networked AUTOSAR-compliant systems. 331-334
• 
  Sriram Narayanan, John Sartori, Rakesh Kumar, Douglas L. Jones:
  Scalable stochastic processors. 335-338

Variability Aware Low Power Design

• 
  Bahman Kheradmand Boroujeni, Christian Piguet, Yusuf Leblebici:
  AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics. 339-344
• 
  Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken:
  On the efficacy of write-assist techniques in low voltage nanoscale SRAMs. 345-350
• 
  Hwisung Jung, Massoud Pedram:
  Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times. 351-356

Performance Estimation and Runtime Management of MPSoCs

• 
  Timon D. ter Braak, Philip K. F. Hölzenspies, Jan Kuper, Johann L. Hurink, Gerard J. M. Smit:
  Run-time spatial resource management for real-time applications on heterogeneous MPSoCs. 357-362
• 
  Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran:
  Rapid runtime estimation methods for pipelined MPSoCs. 363-368
• 
  Jari Kreku, Kari Tiensyrjä, Geert Vanmeerbeeck:
  Automatic workload generation for system-level exploration based on modified GCC compiler. 369-374

Application of Reconfigurable and Adaptive Systems

• 
  Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich:
  A rapid prototyping system for error-resilient multi-processor systems-on-chip. 375-380
• 
  Jih-Sheng Shen, Chun-Hsian Huang, Pao-Ann Hsiung:
  Learning-based adaptation to applications and environments in a reconfigurable Network-on-Chip. 381-386
• 
  Sean Whitty, Henning Sahlbach, Brady Hurlburt, Rolf Ernst, Wolfram Putzke-Röming:
  Application-specific memory performance of a heterogeneous reconfigurable architecture. 387-392
• 
  Abdulkadir Akin, Gokhan Sayilar, Ilker Hamzaoglu:
  A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation. 393-398
• 
  Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu:
  Ultra-high throughput string matching for Deep Packet Inspection. 399-404
• 
  Juan Fernando Eusse Giraldo, Nahri Moreano, Ricardo Pezzuol Jacobi, Alba Cristina Magalhaes Alves de Melo:
  A HMMER hardware accelerator using divergences. 405-410

Wearout and Process Variation Mitigation and Modelling

• 
  Lin Li, Youtao Zhang, Jun Yang, Jianhua Zhao:
  Proactive NBTI mitigation for busy functional units in out-of-order microprocessors. 411-416
• 
  Shrikanth Ganapathy, Ramon Canal, Antonio González, Antonio Rubio:
  Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability. 417-422
• 
  Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
  Analytical model for TDDB-based performance degradation in combinational logic. 423-428
• 
  Bartomeu Alorda, Gabriel Torrens, Sebastià A. Bota, Jaume Segura:
  Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs. 429-434

Model Based Design of Embedded Systems

• 
  Alexander Michailidis, Uwe Spieth, Thomas Ringler, Bernd Hedenetz, Stefan Kowalewski:
  Test front loading in early stages of automotive software development based on AUTOSAR. 435-440
• 
  Purandar Bhaduri, Ingo Stierand:
  A proposal for real-time interfaces in SPEEDS. 441-446
• 
  Kim Guldstrand Larsen, Shuhao Li, Brian Nielsen, Saulius Pusinskas:
  Scenario-based analysis and synthesis of real-time systems using uppaal. 447-452

Extraction and Model Order Reduction

• 
  Tarek A. El-Moselhy, Luca Daniel:
  Variation-aware interconnect extraction using statistical moment preserving model order reduction. 453-458
• 
  Navin Srivastava, Roberto Suaya, Kaustav Banerjee:
  Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. 459-464
• 
  Jorge Fernandez Villena, Luís Miguel Silveira:
  HORUS - high-dimensional Model Order Reduction via low moment-matching upgraded sampling. 465-470
• 
  Maria V. Ugryumova, Wil H. A. Schilders:
  On passivity of the super node algorithm for EM modeling of interconnect systems. 471-476

Panel

• 
  Gerhard P. Fettweis:
  The road to energy-efficient systems: From hardware-driven to software-defined. 477

Automating Verification with Simulation, Properties and Assertions

• 
  Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli:
  Vacuity analysis for property qualification by mutation of checkers. 478-483
• 
  Tao Zhang, Tao Lv, Xiaowei Li:
  An abstraction-guided simulation approach using Markov models for microprocessor verification. 484-489
• 
  Mingsong Chen, Xiaoke Qin, Prabhat Mishra:
  Efficient decision ordering techniques for SAT-based test generation. 490-495
• 
  Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
  DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. 496-501

Power Optimization and Estimation for Flash and CMOS Technologies

• 
  Vidyabhushan Mohan, Sudhanva Gurumurthi, Mircea R. Stan:
  FlashPower: A detailed power model for NAND flash memory. 502-507
• 
  Wei Gao, Richard Hornsey:
  A power optimization method for CMOS Op-Amps using sub-space based geometric programming. 508-513
• 
  Sin-Yu Chen, Rung-Bin Lin, Hui-Hsiang Tung, Kuen-Wey Lin:
  Power gating design for standard-cell-like structured ASICs. 514-519
• 
  Meng Tie, Haiying Dong, Tong Wang, Xu Cheng:
  Dual-Vth leakage reduction with Fast Clock Skew Scheduling Enhancement. 520-525

Automotive Systems: Mastering Complexity and Uncertainty

• 
  Luca Fanucci, Giuseppe Pasetti, Paolo D'Abramo, Riccardo Serventi, Francesco Tinfena, Pierre Chassard, L. Labiste, Pierre Tisserand:
  An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability. 526-531
• 
  Matthias Müller, Axel G. Braun, Joachim Gerlach, Wolfgang Rosenstiel, Dennis Nienhüser, Johann Marius Zöllner, Oliver Bringmann:
  Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation. 532-537
• 
  Andreas Braun, Oliver Bringmann, Djones Lettnin, Wolfgang Rosenstiel:
  Simulation-based verification of the MOST NetInterface specification revision 3.0. 538-543
• 
  Michael Karner, Eric Armengaud, Christian Steger, Reinhold Weiss:
  Holistic simulation of FlexRay networks by using run-time model switching. 544-549
• 
  Arkadeb Ghosal, Haibo Zeng, Marco Di Natale, Yakov Ben-Haim:
  Computing robustness of FlexRay schedules to uncertainties in design parameters. 550-555

Embedded Tutorial - Adaptive Testing

• 
  Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli:
  Adapting to adaptive testing. 556-561

Virtualization Technologies

• 
  Ernest Artiaga, Toni Cortes:
  Using filesystem virtualization to avoid metadata bottlenecks. 562-567
• 
  Zhe-Mao Hsu, Jen-Chieh Yeh, I-Yao Chuang:
  An accurate system architecture refinement methodology with mixed abstraction-level virtual platform. 568-573
• 
  Matthias Bolte, Michael Sievers, Georg Birkenheuer, Oliver Niehörster, André Brinkmann:
  Non-intrusive virtualization management using libvirt. 574-579

Variability Reliability and Thermal Trade-Offs for Low-Power Design

• 
  Cheng Zhuo, Dennis Sylvester, David T. Blaauw:
  Process variation and temperature-aware reliability management. 580-585
• 
  Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra:
  Optimized self-tuning for circuit aging. 586-591
• 
  Andrew J. Ricketts, Jawar Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, Dhiraj K. Pradhan:
  Investigating the impact of NBTI on different power saving cache strategies. 592-597

Interactive Presentations

• 
  Wang Huan, Zhang Yang, Mei Chen, Ling Ming:
  Energy-oriented dynamic SPM allocation based on time-slotted Cache conflict graph. 598-601
• 
  Wei Liu, Ying Tan, Qinru Qiu:
  Enhanced Q-learning algorithm for dynamic power management with performance constraint. 602-605
• 
  Aline Mello, Isaac Maia, Alain Greiner, François Pêcheux:
  Parallel simulation of systemC TLM 2.0 compliant MPSoC on SMP workstations. 606-609
• 
  István Haller, Zoltan Francisc Baruch:
  High-speed clock recovery for low-cost FPGAs. 610-613
• 
  Uwe Proß, Sebastian Goller, Erik Markert, Michael Jüttner, Jan Langer, Ulrich Heinkel, Joachim Knäblein, Axel Schneider:
  Demonstration of an in-band reconfiguration data distribution and network node reconfiguration. 614-617
• 
  Julio César Vázquez, Víctor H. Champac, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira:
  Programmable aging sensor for automotive safety-critical applications. 618-621
• 
  Zohaib Mahmood, Bradley N. Bond, Tarek Moselhy, Alexandre Megretski, Luca Daniel:
  Passive reduced order modeling of multiport interconnects via semidefinite programming. 622-625
• 
  Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson:
  GoldMine: Automatic assertion generation using data mining and static analysis. 626-629
• 
  Marcio Ferreira da Silva Oliveira, Henning Zabel, Wolfgang Müller:
  Assertion-based verification of RTOS properties. 630-633
• 
  Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino:
  Post-placement temperature reduction techniques. 634-637
• 
  Jithendra Srinivas, Sukumar Jairam:
  Clock gating approaches by IOEX graphs and cluster efficiency plots. 638-641
• 
  Kay Klobedanz, Christoph Kuznik, Andreas Thuy, Wolfgang Müller:
  Timing modeling and analysis for AUTOSAR-based software development - a case study. 642-645
• 
  Timo Kerstan, Markus Oertel:
  Design of a real-time optimized emulation method. 646-649
• 
  Binjie Cheng, Daryoosh Dideban, Negin Moezi, Campbell Millar, Gareth Roy, Xingsheng Wang, Scott Roy, Asen Asenov:
  Capturing intrinsic parameter fluctuations using the PSP compact model. 650-653
• 
  Pavel Ghosh, Arunabha Sen:
  Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective. 654-657

Cool Sensor Networks (Cool Electronic Systems Day)

• 
  Jan M. Rabaey:
  Always energy-optimal microscopic wireless systems. 658
• 
  Hendrik Ahlendorf, Lars Gopfert:
  Hardware / software design challenges of low-power sensor nodes for condition monitoring. 659
• 
  Ron Barker:
  Security aspects in 6lowPan networks. 660

HOT TOPIC - Memristor: Device, Design and Application

• 
  Dmitri B. Strukov, Alan Mishchenko:
  Monolithically stackable hybrid FPGA. 661-666
• 
  Xiaobin Wang, Yiran Chen:
  Spintronic memristor devices and application. 667-672
• 
  Hai Li, Miao Hu:
  Compact model of memristors and its application in computing systems. 673-678

Addressing the Challenge of Technology Scaling

• 
  Daniele Ludovici, Alessandro Strano, Georgi Nedeltchev Gaydadjiev, Luca Benini, Davide Bertozzi:
  Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. 679-684
• 
  Carles Hernández, Federico Silla, José Duato:
  A methodology for the characterization of process variation in NoC links. 685-690
• 
  Johnnie Chan, Gilbert Hendry, Aleksandr Biberman, Keren Bergman, Luca P. Carloni:
  PhoenixSim: A simulator for physical-layer analysis of chip-scale photonic interconnection networks. 691-696

Analogue and Mixed-Signal System Implementations

• 
  Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx:
  An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. 697-701
• 
  Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels:
  A compact digital amplitude modulator in 90nm CMOS. 702-705
• 
  Thomas Froehlich, Vivek Sharma, Markus Bingesser:
  A 14 bit, 280 kS/s cyclic ADC with 100 dB SFDR. 706-710
• 
  Armin Tajalli, Yusuf Leblebici:
  Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits. 711-716

On-Line Testing Techniques

• 
  Kai-Chiang Wu, Diana Marculescu:
  Clock skew scheduling for soft-error-tolerant sequential circuits. 717-722
• 
  Mario Schölzel:
  HW/SW co-detection of transient and permanent faults with fast recovery in statically scheduled data paths. 723-728
• 
  Kedar Karmarkar, Spyros Tragoudas:
  Scalable codeword generation for coupled buses. 729-734
• 
  Ching-Yi Chen, Cheng-Wen Wu:
  An adaptive code rate EDAC scheme for random access memory. 735-740

Performance Analysis of Embedded Software for MPSoCs

• 
  Rodolfo Pellizzoni, Andreas Schranzhofer, Jian-Jia Chen, Marco Caccamo, Lothar Thiele:
  Worst case delay analysis for memory interference in multicore systems. 741-746
• 
  Sjoerd Meijer, Hristo Nikolov, Todor P. Stefanov:
  Throughput modeling to evaluate process merging transformations in polyhedral process networks. 747-752
• 
  Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
  Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. 753-758
• 
  Simon Schliecker, Mircea Negrean, Rolf Ernst:
  Bounding the shared resource load for the performance analysis of multiprocessor systems. 759-764

Advances in Logic Synthesis for Reliability and Matching

• 
  Melinda Y. Agyekum, Steven M. Nowick:
  An error-correcting unordered code and hardware support for robust asynchronous global communication. 765-770
• 
  Hadi Katebi, Igor L. Markov:
  Large-scale Boolean matching. 771-776
• 
  Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, André Inácio Reis:
  KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. 777-782
• 
  Samuel B. Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He:
  RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. 783-788

Panel

• 
  Grant Martin, Albrecht Mayer:
  Panel 6.8: The challenges of heterogeneous multicore debug. 789

Keynote Address

• 
  Mark Horowitz:
  Why design must change: Rethinking digital design. 791

Cool Communications Systems (Cool Electronic Systems Day)

• 
  Wolfgang Raab, Jörg Berthold, J. A. Ulrich Hachmann, Dominik Langen, Michael Schreiner, Holger Eisenreich, Jens-Uwe Schluessler, Georg Ellguth:
  Low power design of the X-GOLD® SDR 20 baseband processor. 792-793
• 
  Volker Aue:
  Low power mobile internet devices using LTE technology. 794

Statistical Validation at 45nm and Beyond

• 
  Michael Wieckowski, Dennis Sylvester, David T. Blaauw, Vikas Chandra, Sachin Idgunji, Cezary Pietrzyk, Robert C. Aitken:
  A black box method for stability analysis of arbitrary SRAM cell structures. 795-800
• 
  Masood Qazi, Mehul Tikekar, Lara Dolecek, Devavrat Shah, Anantha P. Chandrakasan:
  Loop flattening & spherical sampling: Highly efficient model reduction techniques for SRAM yield analysis. 801-806
• 
  Javid Jaffari, Mohab Anis:
  Practical Monte-Carlo based timing yield estimation of digital circuits. 807-812
• 
  Yashodhan Kanoria, Subhasish Mitra, Andrea Montanari:
  Statistical static timing analysis using Markov chain Monte Carlo. 813-818

Reconfigurable Architectures

• 
  Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel:
  KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. 819-824
• 
  Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque:
  A reconfigurable cache memory with heterogeneous banks. 825-830
• 
  Kamana Sigdel, Mark Thompson, Carlo Galuzzi, Andy D. Pimentel, Koen Bertels:
  Evaluation of runtime task mapping heuristics with rSesame - a case study. 831-836
• 
  Abelardo Jara-Berrocal, Ann Gordon-Ross:
  VAPRES: A Virtual Architecture for Partially Reconfigurable Embedded Systems. 837-842

Secure Embedded Systems

• 
  Zhimin Chen, Patrick Schaumont:
  pSHS: A scalable parallel software implementation of Montgomery multiplication for multicore systems. 843-848
• 
  Maxime Nassar, Shivam Bhasin, Jean-Luc Danger, Guillaume Duc, Sylvain Guilley:
  BCDL: A high speed balanced DPL for FPGA with global precharge and no early evaluation. 849-854
• 
  Andrea Pellegrini, Valeria Bertacco, Todd M. Austin:
  Fault-based attack of RSA authentication. 855-860
• 
  Abhishek Das, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
  Detecting/preventing information leakage on the memory bus due to malicious hardware. 861-866
• 
  Josep Balasch, Ingrid Verbauwhede, Bart Preneel:
  An embedded platform for privacy-friendly road charging applications. 867-872

Test Generation, Fault Simulation and Diagnosis

• 
  S. Balatsouka, Vasileios Tenentes, Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
  Defect aware X-filling for low-power scan testing. 873-878
• 
  Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
  Parallel X-fault simulation with critical path tracing technique. 879-884
• 
  Jing Ye, Yu Hu, Xiaowei Li:
  Diagnosis of multiple arbitrary faults with mask and reinforcement effect. 885-890

Applications and Principles for Embedded Multi-Core Systems

• 
  Arquimedes Canedo, Takeo Yoshizawa, Hideaki Komatsu:
  Skewed pipelining for parallel simulink simulations. 891-896
• 
  Alessio Bonfietti, Luca Benini, Michele Lombardi, Michela Milano:
  An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms. 897-902
• 
  Reimund Klemm, Gerhard P. Fettweis:
  Bitstream processing for embedded systems using C++ metaprogramming. 909-913

Innovative Memory Architectures

• 
  Alexandre Peixoto Ferreira, Miao Zhou, Santiago Bock, Bruce R. Childers, Rami G. Melhem, Daniel Mossé:
  Increasing PCM main memory lifetime. 914-919
• 
  Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran:
  Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. 920-925
• 
  Heeyeol Yu:
  A memory- and time-efficient on-chip TCAM minimizer for IP lookup. 926-931

Panel

• 
  Wolfgang Ecker, Pierre Bricaud, Rainer Dömer, Yossi Veller, Stefan Heinen, Jürgen Mössinger, Andreas von Schwerin:
  Panel Session - Who Is Closing the embedded software design gap? 932

Interactive Presentations

• 
  Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li:
  Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs. 933-936
• 
  Giuseppe Pasetti, Luca Fanucci, Riccardo Serventi:
  A High-Voltage Low-Power DC-DC buck regulator for automotive applications. 937-940
• 
  Jesung Kim, Soontae Kim, Yebin Lee:
  SimTag: Exploiting tag bits similarity to improve the reliability of the data caches. 941-944
• 
  Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera:
  The split register file. 945-948
• 
  Daniel Baudisch, Jens Brandt, Klaus Schneider:
  Multithreaded code from synchronous programs: Extracting independent threads for OpenMP. 949-952
• 
  Nabeel Iqbal, Muhammad Adnan Siddique, Jörg Henkel:
  RMOT: Recursion in model order for task execution time estimation in a software pipeline. 953-956
• 
  Doochul Shin, Sandeep K. Gupta:
  Approximate logic synthesis for error tolerant applications. 957-960
• 
  Marc Galceran Oms, Jordi Cortadella, Dmitry Bufistov, Michael Kishinevsky:
  Automatic microarchitectural pipelining. 961-964
• 
  Rahul Rithe, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha P. Chandrakasan:
  Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage. 965-968
• 
  Stephan Wong, Fakhar Anjam, Faisal Nadeem:
  Dynamically reconfigurable register file for a softcore VLIW processor. 969-972
• 
  Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
  FPGA-based adaptive computing for correlated multi-stream processing. 973-976
• 
  Olivier Meynard, Sylvain Guilley, Jean-Luc Danger, Laurent Sauvage:
  Far Correlation-based EMA with a precharacterized leakage model. 977-980
• 
  Masami Izumi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta:
  Improved countermeasure against Address-bit DPA for ECC scalar multiplication. 981-984
• 
  Mohammad Hossein Neishaburi, Zeljko Zilic:
  Enabling efficient post-silicon debug by clustering of hardware-assertions. 985-988
• 
  Patrick Bellasi, Stefano Bosisio, Matteo Carnevali, William Fornaciari, David Siorpaes:
  Constrained Power Management: Application to a multimedia mobile platform. 989-992
• 
  Farhad Mehdipour, Hiroaki Honda, Hiroshi Kataoka, Koji Inoue, Irina Kataeva, Kazuaki J. Murakami, Hiroyuki Akaike, Akira Fujimaki:
  Mapping scientific applications on a large-scale data-path accelerator implemented by single-flux quantum (SFQ) circuits. 993-996
• 
  Tamar Kranenburg, Rene van Leuken:
  MB-LITE: A robust, light-weight soft-core implementation of the MicroBlaze architecture. 997-1000
• 
  Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
  Automatic pipelining from transactional datapath specifications. 1001-1004

Cool Computing Platforms (Cool Electronic Systems Day)

• 
  Chris Schläger:
  Increasing the power efficiency of PCs by improving the hardware/OS interaction. 1005
• 
  Krisztián Flautner:
  Optimize your power and performance yields and regain those sleepless nights. 1006
• 
  Manfred Dietrich, Uwe Eichler, Joachim Haase:
  Digital statistical analysis using VHDL. 1007-1010

HOT TOPIC - Cross-Layer Optimization to Address the Dual Challenges of Energy and Reliability

• 
  Sani R. Nassif, Nikil Mehta, Yu Cao:
  A resilience roadmap. 1011-1016
• 
  André DeHon, Heather M. Quinn, Nicholas P. Carter:
  Vision for cross-layer optimization to address the dual challenges of energy and reliability. 1017-1022
• 
  Nicholas P. Carter, Helia Naeimi, Donald S. Gardner:
  Design techniques for cross-layer resilience. 1023-1028
• 
  Subhasish Mitra, Kevin Brelsford, Pia N. Sanda:
  Cross-layer resilience challenges: Metrics and optimization. 1029-1034

System Modeling for Design Space Exploration and Validation

• 
  Jun Zhu, Ingo Sander, Axel Jantsch:
  Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. 1035-1040
• 
  Yang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal:
  Automated bottleneck-driven design-space exploration of media processing systems. 1041-1046
• 
  Markus Damm, Javier Moreno, Jan Haase, Christoph Grimm:
  Using Transaction Level Modeling techniques for wireless sensor network simulation. 1047-1052
• 
  Markus Becker, Giuseppe Di Guglielmo, Franco Fummi, Wolfgang Müller, Graziano Pravadelli, Tao Xie:
  RTOS-aware refinement for TLM2.0-based HW/SW designs. 1053-1058

Sensor Networks and Security Technology

• 
  Yang Li, Kazuo Sakiyama, Lejla Batina, Daisuke Nakatsu, Kazuo Ohta:
  Power Variance Analysis breaks a masked ASIC implementation of AES. 1059-1064
• 
  Xiaoxiao Wang, Mohammad Tehranipoor:
  Novel Physical Unclonable Function with process and environmental variations. 1065-1070
• 
  Daniela De Venuto, Eduard F. Stikvoort, David Tio Castro, Youri Ponomarev:
  Ultra low-power 12-bit SAR ADC for RFID applications. 1071-1075
• 
  Massimo Cutrupi, Marco Crepaldi, Mario R. Casu, Mariagrazia Graziano:
  A flexible UWB Transmitter for breast cancer detection imaging systems. 1076-1081
• 
  Chun-Ming Lo, Tsung-Ching Huang, Cheng-Yi Chiang, Johnson Hou, Kwang-Ting Cheng:
  A portable multi-pitch e-drum based on printed flexible pressure sensors. 1082-1087

Variability and Yield in Analogue and Mixed-Signal Design

• 
  Daniel Mueller-Gritschneder, Helmut Graeb:
  Computation of yield-optimized Pareto fronts for analog integrated circuit specifications. 1088-1093
• 
  Elie Maricau, Georges G. E. Gielen:
  Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity. 1094-1099
• 
  Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu, Arun Bhanu:
  A general mathematical model of probabilistic ripple-carry adders. 1100-1105
• 
  Bo Liu, Francisco V. Fernández, Georges G. E. Gielen:
  An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique. 1106-1111

Resource-Aware Embedded Code Optimization

• 
  Li Wang, Jingling Xue, Xuejun Yang:
  Reuse-aware modulo scheduling for stream processors. 1112-1117
• 
  Weijia Che, Amrit Panda, Karam S. Chatha:
  Compilation of stream programs for multicore processors that incorporate scratchpad memories. 1118-1123
• 
  Hideki Takase, Hiroyuki Tomiyama, Hiroaki Takada:
  Partitioning and allocation of scratch-pad memory for priority-based preemptive multi-task systems. 1124-1129
• 
  Yuanrui Zhang, Lanping Deng, Praveen Yedlapalli, Sai Prashanth Muralidhara, Hui Zhao, Mahmut T. Kandemir, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun:
  A special-purpose compiler for look-up table and code generation for function evaluation. 1130-1135

Macromodelling for Thermal and Interconnect Systems

• 
  Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Eduardo H. Pacheco, Murli Tirumala:
  General behavioral thermal modeling and characterization for multi-core microprocessor design. 1136-1141
• 
  Alessandro Chinea, Stefano Grivet-Talocia, Dirk Deschrijver, Tom Dhaene, Luc Knockaert:
  On the construction of guaranteed passive macromodels for high-speed channels. 1142-1147
• 
  Zuochang Ye, L. Miguel Silveira, Joel R. Phillips:
  Extended Hamiltonian Pencil for passivity assessment and enforcement for S-parameter systems. 1148-1152
• 
  Takayuki Watanabe, Hideki Asai:
  Equivalent circuit modeling of multilayered power/ground planes for fast transient simulation. 1153-1158

Embedded Tutorial - More Moore and Beyond CMOS (Nanoelectronics Day)

• 
  Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra:
  Carbon nanotube circuits: Living with imperfections and variations. 1159-1164

Multi-Level, Multi-Domain System Simulation

• 
  Xi Chen, Robert P. Dick, Li Shang:
  Properties of and improvements to time-domain dynamic thermal analysis algorithms. 1165-1170
• 
  Stefan Lämmermann, Jürgen Ruf, Thomas Kropf, Wolfgang Rosenstiel, Alexander Viehl, Alexander Jesser, Lars Hedrich:
  Towards assertion-based verification of heterogeneous system designs. 1171-1176
• 
  Meng-Huan Wu, Wen-Chuan Lee, Chen-Yu Chuang, Ren-Song Tsay:
  Automatic generation of software TLM in multiple abstraction layers for efficient HW/SW co-simulation. 1177-1182
• 
  Rauf Salimi Khaligh, Martin Radetzki:
  Modeling constructs and kernel for parallel simulation of accuracy adaptive TLMs. 1183-1188

Language Based Approaches to System Level Design

• 
  Christian Zebelein, Joachim Falk, Christian Haubelt, Jürgen Teich, Rainer Dorsch:
  Efficient High-Level modeling in the networking domain. 1189-1194
• 
  Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, Jean-Philippe Diguet, Philippe Soulard:
  UML design for dynamically reconfigurable multiprocessor embedded systems. 1195-1200
• 
  Fabian Mischkalla, Da He, Wolfgang Müller:
  Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems. 1201-1206
• 
  Luca Ferro, Laurence Pierre:
  Formal semantics for PSL modeling layer and application to the verification of transactional models. 1207-1212

Space and Aeronautics Avionics Application Design

• 
  Michel Pignol:
  COTS-based applications in space avionics. 1213-1219
• 
  Henri Bauer, Jean-Luc Scharbarg, Christian Fraboul:
  Worst-case end-to-end delay analysis of an avionics AFDX network. 1220-1224
• 
  Claude Sarno, Christian Tantolin:
  Integration, cooling and packaging issues for aerospace equipments. 1225-1230
• 
  Luca Sterpone, Niccolò Battezzati:
  A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs. 1231-1236

Design for Test, Diagnosis, and Yield

• 
  Irith Pomeranz, Sudhakar M. Reddy:
  Reducing the storage requirements of a test sequence by using a background vector. 1237-1242
• 
  Melanie Elm, Hans-Joachim Wunderlich:
  BISD: Scan-based Built-In self-diagnosis. 1243-1248
• 
  Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta:
  Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. 1249-1254

High Level Synthesis

• 
  Jason Cong, Hui Huang, Wei Jiang:
  A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. 1255-1260
• 
  Junbo Yu, Qiang Zhou, Gang Qu, Jinian Bian:
  Behavioral level dual-vth design for reduced leakage power with thermal awareness. 1261-1266
• 
  Jason Cong, Bin Liu, Junjuan Xu:
  Coordinated resource optimization in behavioral synthesis. 1267-1272

Physical Design Potpourri: DFM, Delay Modeling and Floorplanning

• 
  Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky:
  A methodology for propagating design tolerances to shape tolerances for use in manufacturing. 1273-1278
• 
  Xin Gao, Luca Macchiarulo:
  Enhancing double-patterning detailed routing with lazy coloring and within-path conflict avoidance. 1279-1284
• 
  Safar Hatami, Massoud Pedram:
  Efficient representation, stratification, and compression of variational CSM library waveforms using Robust Principle Component Analysis. 1285-1290
• 
  Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni:
  Exploiting local logic structures to optimize multi-core SoC floorplanning. 1291-1296

Interactive Presentations

• 
  Sven van Haastregt, Eyal Halm, Bart Kienhuis:
  Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems. 1297-1300
• 
  Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres, Michel Robert:
  Differential Power Analysis enhancement with statistical preprocessing. 1301-1304
• 
  Javid Jaffari, Mohab Anis:
  Correlation controlled sampling for efficient variability analysis of analog circuits. 1305-1308
• 
  Rajeev Narayanan, Behzad Akbarpour, Mohamed H. Zaki, Sofiène Tahar, Lawrence C. Paulson:
  Formal verification of analog circuits in the presence of noise and process variation. 1309-1312
• 
  Asma Charfi, Chokri Mraidha, Sébastien Gérard, François Terrier, Pierre Boulet:
  Toward optimized code generation through model-based optimization. 1313-1316
• 
  Ruirui Gu, Alessandro Forin, Richard Neil Pittman:
  Path-based scheduling in a hardware compiler. 1317-1320
• 
  Yung-Shou Cheng, Yen-Cheng Lai, Ruey-Beei Wu:
  Optimization of FIR filter to improve eye diagram for general transmission line systems. 1321-1324
• 
  Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen:
  On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. 1325-1328
• 
  Jun-Kuei Zeng, Chung-Ping Chen:
  Interconnect delay and slew metrics using the beta distribution. 1329-1332
• 
  Yonghyun Hwang, Gunar Schirner, Samar Abdi, Daniel D. Gajski:
  Accurate timed RTOS model for transaction level modeling. 1333-1336
• 
  Kouichi Ono, Manabu Toyota, Ryo Kawahara, Yoshifumi Sakamoto, Takeo Nakada, Naoaki Fukuoka:
  A modeling method by eliminating execution traces for performance evaluation. 1337-1340
• 
  Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler:
  Verifying UML/OCL models using Boolean satisfiability. 1341-1344
• 
  Franck Koebel, Jean-François Coldefy:
  SCOC3: a space computer on a chip. 1345-1348
• 
  Clinton K. Landrock, Bozena Kaminska:
  High temperature polymer capacitors for aerospace applications. 1349-1352
• 
  Songwei Pei, Huawei Li, Xiaowei Li:
  An on-chip clock generation scheme for faster-than-at-speed delay testing. 1353-1356
• 
  George Economakos, Sotirios Xydis, Ioannis Koutras, Dimitrios Soudris:
  Construction of dual mode components for reconfiguration aware high-level synthesis. 1357-1360
• 
  Jesús M. Pérez, Pablo Sánchez, Víctor Fernández:
  Optimizing Data-Flow Graphs with min/max, adding and relational operations. 1361-1364
• 
  Jieyi Long, Seda Ogrenci Memik:
  Optimization of the bias current network for accurate on-chip thermal monitoring. 1365-1368
• 
  Fan Yang, Yici Cai, Qiang Zhou, Jiang Hu:
  SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. 1369-1372
• 
  Elif Alpaslan, Jennifer Dworak, Bram Kruseman, Ananta K. Majhi, Wilmar M. Heuvelman, Paul van de Wiel:
  NIM- a noise index model to estimate delay discrepancies between silicon and simulation. 1373-1376

Panel

• 
  Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Piero Perlo, Andreas Wild, Roberto Zafalon:
  Panel: First commandment at least, do nothing well! 1377

Characterizing and Optimizing NoC Performance

• 
  Natalie D. Enright Jerger:
  SigNet: Network-on-chip filtering for coarse vector directories. 1378-1383
• 
  Akbar Sharifi, Hui Zhao, Mahmut T. Kandemir:
  Feedback control for providing QoS in NoC based multicores. 1384-1389
• 
  Minje Jun, Sungroh Yoon, Eui-Young Chung:
  Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network. 1390-1395

Architectures for Next Generation Wireless Communication

• 
  Teo Cupaiuolo, Massimiliano Siti, Alessandro Tomasoni:
  Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector. 1396-1401
• 
  Özgün Paker, Sebastian Eckert, Andreas Bury:
  A low cost multi-standard near-optimal soft-output sphere decoder: Algorithm and architecture. 1402-1407
• 
  Rudy Beraha, Isask'har Walter, Israel Cidon, Avinoam Kolodny:
  Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study. 1408-1413
• 
  Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo, Ting Chen:
  Domain specific architecture for next generation wireless communication. 1414-1419
• 
  Matthias May, Thomas Ilnseher, Norbert Wehn, Wolfgang Raab:
  A 150Mbit/s 3GPP LTE Turbo code decoder. 1420-1425

Advances in Delay Fault Testing

• 
  Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor, Krishnendu Chakrabarty:
  High-quality pattern selection for screening small-delay defects considering process variations and crosstalk. 1426-1431
• 
  Xiao Liu, Yubin Zhang, Feng Yuan, Qiang Xu:
  Layout-aware pseudo-functional testing for critical paths considering power supply noise effects. 1432-1437
• 
  Irith Pomeranz, Sudhakar M. Reddy:
  On reset based functional broadside tests. 1438-1443

Optimizations of Fault Tolerant and Time Constrained Embedded and Cyber- Physical Systems

• 
  Yu Liu, Han Liang, Kaijie Wu:
  Scheduling for energy efficiency and fault tolerance in hard real-time systems. 1444-1449
• 
  Roy Shea, Mani B. Srivastava, Young Cho:
  Scoped identifiers for efficient bit aligned logging. 1450-1455
• 
  Cristian Ferent, Varun Subramanian, Michael Gilberti, Alex Doboli:
  Linear programming approach for performance-driven data aggregation in networks of embedded sensors. 1456-1461
• 
  Rishad A. Shafik, Bashir M. Al-Hashimi, Krishnendu Chakrabarty:
  Soft error-aware design optimization of low power and time-constrained embedded systems. 1462-1467

Advanced Clocking Strategies

• 
  Dongjin Lee, Igor L. Markov:
  Contango: Integrated optimization of SoC clock networks. 1468-1473
• 
  Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang:
  Clock skew optimization considering complicated power modes. 1474-1479
• 
  Menghao Su, Yunji Chen, Xiang Gao:
  A general method to make multi-clock system deterministic. 1480-1485

Panel

• 
  Érika F. Cota:
  Embedded software testing: What kind of problem is this? 1486

Keynote

• 
  Dimitri A. Antoniadis:
  Nanoelectronics challenges for the 21st century. 1487

Hot Topic

• 
  Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki:
  Cool MPSoC programming. 1488-1493

Industrially-Oriented Formal Verification

• 
  Hong-Zu Chou, Haiqian Yu, Kai-Hui Chang, Dylan Dobbyn, Sy-Yen Kuo:
  Finding reset nondeterminism in RTL designs - scalable X-analysis methodology and case study. 1494-1499
• 
  Kecheng Hao, Fei Xie, Sandip Ray, Jin Yang:
  Optimizing equivalence checking for behavioral synthesis. 1500-1505
• 
  Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg:
  Checking and deriving module paths in Verilog cell library descriptions. 1506-1511
• 
  Lei Bu, You Li, Linzhang Wang, Xin Chen, Xuandong Li:
  BACH 2 : Bounded reachability checker for compositional linear hybrid systems. 1512-1517

Sensor Networks and Applications

• 
  A. Ravinagarajan, Denis Dondi, Tajana Simunic Rosing:
  DVFS based task scheduling in a harvesting WSN for Structural Health Monitoring. 1518-1523
• 
  Jeffrey Boyd, Hari Sundaram, Aviral Shrivastava:
  Power-accuracy tradeoffs in human activity transition detection. 1524-1529
• 
  Wei Chen, Idowu Ayoola, Sidarto Bambang-Oetomo, Loe M. G. Feijs:
  Non-invasive blood oxygen saturation monitoring for neonates using reflectance pulse oximeter. 1530-1535
• 
  Giovanni Diraco, Alessandro Leone, Pietro Siciliano:
  An active vision system for fall detection and posture recognition in elderly healthcare. 1536-1541
• 
  Fabio Vergari, Sara Bartolini, Federico Spadini, Alfredo D'Elia, Guido Zamagni, Luca Roffia, Tullio Salmon Cinotti:
  A Smart Space application to dynamically relate medical and environmental information. 1542-1547
• 
  Aly A. Syed, Johan Lukkien, Roxana Frunza:
  An architecture for self-organization in pervasive systems. 1548-1553

Fault Tolerance

• 
  Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken:
  TIMBER: Time borrowing and error relaying for online timing error resilience. 1554-1559
• 
  Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, Subhasish Mitra:
  ERSA: Error Resilient System Architecture for probabilistic applications. 1560-1565
• 
  Lei Zhang, Yue Yu, Jianbo Dong, Yinhe Han, Shangping Ren, Xiaowei Li:
  Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors. 1566-1571
• 
  Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson:
  Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. 1572-1577

Synthesis and Optimisation of MPSoCs

• 
  Martin Lukasiewycz, Michael Glaß, Jürgen Teich:
  Robust design of embedded systems. 1578-1583
• 
  Lin Huang, Qiang Xu:
  Energy-efficient task allocation and scheduling for multi-mode MPSoCs under lifetime reliability constraint. 1584-1589
• 
  Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang:
  PM-COSYN: PE and memory co-synthesis for MPSoCs. 1590-1595
• 
  Brett H. Meyer, Adam S. Hartman, Donald E. Thomas:
  Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs. 1596-1601

Mixed-Technology and Analogue Design

• 
  Chao Lu, Sang Phill Park, Vijay Raghunathan, Kaushik Roy:
  Efficient power conversion for ultra low voltage micro scale energy transducers. 1602-1607
• 
  Stephan Schulz, Jörg Becker, Thomas Uhle, Karsten Einwich, Sören Sonntag:
  Transmitting TLM transactions over analogue wire models. 1608-1613
• 
  Metha Jeeradit, Jaeha Kim, Mark Horowitz:
  Intent-leveraged optimization of analog circuits via homotopy. 1614-1619

Panel

• 
  Mehdi Baradaran Tahoori, Ishwar Parulkar, Dan Alexandrescu, Kevin Granlund, Allan Silburt, Bapi Vinnakota:
  Panel: Reliability of data centers: Hardware vs. software. 1620

Interactive Presentations

• 
  Fahimeh Jafari, Zhonghai Lu, Axel Jantsch, Mohammad Hossien Yaghmaee:
  Optimal regulation of traffic flows in networks-on-chip. 1621-1624
• 
  Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
  A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. 1625-1628
• 
  Sahar Foroutan, Yvain Thonnart, Richard Hersemeule, Ahmed Jerraya:
  An analytical method for evaluating Network-on-Chip performance. 1629-1632
• 
  Nariman Moezzi Madani, Thorlindur Thorolfsson, William Rhett Davis:
  A low-area flexible MIMO detector for WiFi/WiMAX standards. 1633-1636
• 
  Yu Lee, Ching-Yuan Yang, Nai-Chen Daniel Cheng, Ji-Jan Chen:
  An embedded wide-range and high-resolution CLOCK jitter measurement circuit. 1637-1640
• 
  Alvaro Gómez, Ricard Sanahuja, Luz Balado, Joan Figueras:
  Analog circuit test based on a digital signature. 1641-1644
• 
  Nabeel Iqbal, Muhammad Adnan Siddique, Jörg Henkel:
  DAGS: Distribution agnostic sequential Monte Carlo scheme for task execution time estimation. 1645-1648
• 
  Manoj G. Dixit, Pallab Dasgupta, S. Ramesh:
  Taming the component timing: A CBD methodology for real-time embedded systems. 1649-1652
• 
  Sidharta Andalam, Partha S. Roop, Alain Girault:
  Deterministic, predictable and light-weight multithreading using PRET-C. 1653-1656
• 
  Jieyi Long, Seda Ogrenci Memik:
  Inversed Temperature Dependence aware clock skew scheduling for sequential circuits. 1657-1660
• 
  Priti Aghera, Dilip Krishnaswamy, Diana Fang, Ayse K. Coskun, Tajana Rosing:
  DynAHeal: Dynamic energy efficient task assignment for wireless healthcare systems. 1661-1664
• 
  Demid Borodin, Ben H. H. Juurlink:
  Instruction precomputation with memoization for fault detection. 1665-1668
• 
  Maarten Wiggers, Marco Bekooij, Marc Geilen, Twan Basten:
  Simultaneous budget and buffer size computation for throughput-constrained task graphs. 1669-1672
• 
  Xiaoda Pan, Fan Yang, Xuan Zeng, Yangfeng Su:
  An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits. 1673-1676

Panel

• 
  R. De Keersmaeker, Michael L. Roukes, D. Antoinadis, Hugo De Man, George Bourianoff, Michel Brillouët, Lars Samuelson:
  Panel session - great challenges in nanoelectronics and impact on academic research: More than Moore or Beyond CMOS? 1677

Hot Topic - 3D Stacked ICs: Technology, Design and Test

• 
  Armin Klumpp, Peter Ramm, Robert Wieland:
  3D-integration of silicon devices: A key technology for sophisticated products. 1678-1683
• 
  Paul D. Franzon, W. Rhett Davis, Thorlindur Thorolfsson:
  Creating 3D specific systems: Architecture, design and CAD. 1684-1688
• 
  Erik Jan Marinissen:
  Testing TSV-based three-dimensional stacked ICs. 1689-1694

Formal Methods: Advances in Core Technology

• 
  Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus:
  Leveraging dominators for preprocessing QBF. 1695-1700
• 
  Freek Verbeek, Julien Schmaltz:
  Formal specification of networks-on-chips: deadlock and evacuation. 1701-1706
• 
  Alessandro Cimatti, Anders Franzén, Alberto Griggio, Krishnamani Kalyanasundaram, Marco Roveri:
  Tighter integration of BDDs and SMT for Predicate Abstraction. 1707-1712

Video Encoding and Image Processing Techniques

• 
  Muhammad Shafique, Bastian Molkenthin, Jörg Henkel:
  An HVS-based Adaptive Computational Complexity Reduction Scheme for H.264/AVC video encoder using Prognostic Early Mode Exclusion. 1713-1718
• 
  Davide Anastasia, Yiannis Andreopoulos:
  Scheduling and energy-distortion tradeoffs with operational refinement of image processing. 1719-1724
• 
  Muhammad Shafique, Lars Bauer, Jörg Henkel:
  enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. 1725-1730
• 
  Zdenek Vasícek, Lukás Sekanina, Michal Bidlo:
  A method for design of impulse bursts noise filters optimized for FPGA implementations. 1731-1736
• 
  Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
  Exploration of hardware sharing for image encoders. 1737-1742
• 
  Stavros Hadjitheophanous, Christos Ttofis, Athinodoros S. Georghiades, Theocharis Theocharides:
  Towards hardware stereoscopic 3D reconstruction a real-time FPGA computation of the disparity map. 1743-1748

Video Encoding and Image Processing Techniques

• 
  Jiun-Lang Huang, Kuo-Yu Chou, Ming-Huan Lu, Xuan-Lun Huang:
  A robust ADC code hit counting technique. 1749-1754
• 
  Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada:
  An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links. 1755-1760
• 
  Ke Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir:
  Fault diagnosis of analog circuits based on machine learning. 1761-1766
• 
  Shaji Krishnan, Klaas D. Doornbos, Rudi Brand, Hans G. Kerkhoff:
  Block-level bayesian diagnosis of analogue electronic circuits. 1767-1772

Timing Aspects in System Synthesis

• 
  Eliyah Kilada, Kenneth S. Stevens:
  Control network generator for latency insensitive designs. 1773-1778
• 
  Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik:
  Using Speculative Functional Units in high level synthesis. 1779-1784
• 
  Xue-Yang Zhu:
  Retiming multi-rate DSP algorithms to meet real-time requirement. 1785-1790

Reliability and Power Optimisations for FPGAs

• 
  Qiang Liu, Tim Todman, Wayne Luk:
  Combining optimizations in automated low power design. 1791-1796
• 
  Cristiano Lazzari, Paulo F. Flores, José Monteiro, Luigi Carro:
  A new quaternary FPGA based on a voltage-mode multi-valued circuit. 1797-1802
• 
  Adwait Gupte, Phillip H. Jones:
  An evaluation of a slice fault aware tool chain. 1803-1808
• 
  Assem A. M. Bsoul, Naraig Manjikian, Li Shang:
  Reliability- and process variation-aware placement for FPGAs. 1809-1814