IEEE International Conference on Field-Programmable Technology (FPT 2002) (original) (raw)

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FPT 2002: Hong Kong, China

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  • Keynotes
  • Networking Applications
  • Run-time Reconfiguration Technology
  • Signal and Matrix Processing
  • FPGA-based Applications
  • Reconfigurable and Memory Architectures
  • High-Level Design Tools
  • Reconfigurable Circuits and Devices
  • Technology Mapping and Layout Tools
  • Debugging Methods
  • Instruction Processors and Systems
  • Poster Session

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  Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, FPT 2002, Hong Kong, China, December 16-18, 2002. IEEE 2002, ISBN 0-7803-7574-2

Keynotes

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    Paul Y. S. Cheung:
    Technology research and development in Hong Kong: hype or reality.
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    Tsugio Makimoto:
    The hot decade of field programmable technologies. 3-6
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    Patrick Lysaght:
    FPGAs as meta-platforms for embedded systems. 7-12
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    Michael J. Flynn:
    Programmed solutions: the step beyond programmed logic [computer architecture]. 13-16
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    Paul Master:
    The next big leap in reconfigurable systems. 17-22

Networking Applications

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    Toshiaki Miyazaki, Takahiro Murooka, Noriyuki Takahashi, Masashi Hashimoto:
    Real-time packet editing using reconfigurable hardware for active networking. 26-33
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    Ocean Y. H. Cheung, Philip Heng Wai Leong:
    Implementation of an FPGA based accelerator for virtual private networks. 34-41

Run-time Reconfiguration Technology

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    Arran Derbyshire, Wayne Luk:
    Compiling run-time parametrisable designs. 44-51
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    Tero Rissa, Riku Uusikartano, Jarkko Niittylahti:
    Adaptive FIR filter architectures for run-time reconfigurable FPGAs. 52-59
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    Gareth Lee, George J. Milne:
    A methodology for design of run-time reconfigurable systems. 60-67
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    Usama Malik, Keith So, Oliver Diessel:
    Resource-aware run-time elaboration of behavioural FPGA specifications. 68-75

Signal and Matrix Processing

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    K. S. Yeung, S. C. Chan:
    Multiplier-less FIR digital filters using programmable sum-of-power-of-two (SOPOT) coefficients. 78-84
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    Ying Yi, Roger F. Woods:
    FPGA-based system-level design framework based on the IRIS synthesis tool and System Generator. 85-92
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    Ju-wook Jang, Seonil Choi, Viktor K. Prasanna:
    Area and time efficient implementations of matrix multiplication on FPGAs. 93-100

FPGA-based Applications

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    Dennis K. Y. Tong, Pui Sze Lo, Kin-Hong Lee, Philip Heng Wai Leong:
    A system level implementation of Rijndael on a memory-slot based FPGA card. 102-109
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    John A. Williams, Anwar S. Dawood, Stephen J. Visser:
    FPGA-based cloud detection for real-time onboard remote sensing. 110-116
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    Yohei Hori, Masashi Sonoyama, Tsutomu Maruyama:
    An FPGA-based processor for shogi mating problems. 117-124
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    Michael Guntsch, Martin Middendorf, Bernd Scheuermann, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck, Keith So:
    Population based ant colony optimization on FPGA. 125-132

Reconfigurable and Memory Architectures

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    Derek B. Gottlieb, Jeffrey J. Cook, Joshua D. Walstrom, Steve Ferrera, Chi-Wei Wang, Nicholas P. Carter:
    Clustered programmable-reconfigurable processors. 134-141
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    Steven J. E. Wilton:
    Implementing logic in FPGA memory arrays: heterogeneous memory architectures. 142-147

High-Level Design Tools

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    José Gabriel F. Coutinho, Wayne Luk:
    Optimising and adapting high-level hardware designs. 150-157
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    Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
    Floating-point bitwidth analysis via automatic differentiation. 158-165
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    Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins:
    DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. 166-173
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    Samir Belkacemi, Khaled Benkrid, Danny Crookes:
    HIDE: a logic based hardware intelligent description environment. 174-180

Reconfigurable Circuits and Devices

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    Kuan Zhou, Channakeshav, Michael Chu, Jong-Ru Guo, S.-C. Liu, Russell P. Kraft, Chao You, John F. McDonald:
    Gigahertz SiGe BiCMOS FPGAs with new architectures and novel power management schemes. 182-188
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    Cristina Costa Santini, José F. M. do Amaral, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco, Moisés H. Szwarcman:
    Evolutionary analog circuit design on a programmable analog multiplexer array. 189-196
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    Minoru Watanabe, Fuminori Kobayashi:
    An optically differential reconfigurable gate array and its power consumption estimation. 197-202

Technology Mapping and Layout Tools

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    Shih-Liang Chen, TingTing Hwang, C. L. Liu:
    A technology mapping algorithm for CPLD architectures. 204-210
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    Jason Helge Anderson, Farid N. Najm:
    Power-aware technology mapping for LUT-based FPGAs. 211-218
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    Andy Gean Ye, Jonathan Rose, David M. Lewis:
    Synthesizing datapath circuits for FPGAs with emphasis on area minimization. 219-226
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    Mehrdad Eslami Dehkordi, Stephen Dean Brown:
    The effect of cluster packing and node duplication control in delay driven clustering. 227-233

Debugging Methods

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    Masao Kubo, Masahiro Fujita:
    Debug methodology for arithmetic circuits on FPGAs. 236-242
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    Eric Roesler, Brent E. Nelson:
    Debug methods for hybrid CPU/FPGA systems. 243-250

Instruction Processors and Systems

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    Andreas Fidjeland, Wayne Luk, Stephen H. Muggleton:
    Scalable acceleration of inductive logic programs. 252-259
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    Paul Beckett:
    A fine-grained reconfigurable logic array based on double gate transistors. 260-267
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    Stefan Valentin Gheorghita, Weng-Fai Wong, Tulika Mitra, Surendranath Talla:
    A co-simulation study of adaptive EPIC computing. 268-275
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    Dario L. Sancho-Pradel, Simon R. Jones, Roger Goodall:
    System on programmable chip for real-time control implementations. 276-283

Poster Session

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    César Torres-Huitzil, Selene Maya-Rueda, Miguel O. Arias-Estrada:
    A reconfigurable vision system for real-time applications. 286-289
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    José Luis Núñez, Simon Jones:
    Lossless data compression programmable hardware for high-speed data networks. 290-293
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    Khaled Benkrid:
    A multiplier-less FPGA core for image algebra neighbourhood operations. 294-297
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    Sushil Chandra Jain, Anshul Kumar, Shashi Kumar:
    Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards. 298-301
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    Sui-Tung Mak, Kai-Pui Lam:
    Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing. 302-305
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    Anwar S. Dawood, John A. Williams, Stephen J. Visser:
    On-board satellite image compression using reconfigurable FPGAs. 306-310
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    Máire McLoone, John V. McCanny:
    Efficient single-chip implementation of SHA-384 and SHA-512. 311-314
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    Gwo-Yang Wu, Liang-Bi Chen, Yuan-Long Jeang, Gwo-Jia Jong:
    An optimal PCM codec soft IP generator and its application. 315-317
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    Valeri F. Tomashau:
    Efficient 4-input LUTs FPGA implementation of combinatorial multiplier over canonical base GF(16). 318-321
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    Stephen J. Visser, Anwar S. Dawood, John A. Williams:
    FPGA based real-time adaptive filtering for space applications. 322-326
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    Mehdi Baradaran Tahoori:
    Diagnosis of open defects in FPGA interconnect. 328-331
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    Mehdi Baradaran Tahoori:
    Testing for resistive open defects in FPGAs. 332-335
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    Annamalai Muthukaruppan, Sivaprakasam Suresh, V. Kamakoti:
    A novel three phase parallel genetic approach to routing for field programmable gate arrays. 336-339
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    John Y. H. Ko, Kam-Wing Ng:
    Reconfigurable implementation of radiosity distribution computation. 340-343
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    John Hopf, G. Stewart Von Itzstein, David A. Kearney:
    Hardware Join Java: a high level language for reconfigurable hardware development. 344-347
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    Mark Jasiunas, David A. Kearney, John Hopf, Grant B. Wigley:
    Image fusion for uninhabited airborne vehicles. 348-351
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    T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay:
    Development framework for firewall processors. 352-355
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    Abdsamad Benkrid, Khaled Benkrid, Danny Crookes:
    Design and implementation of a novel architecture for symmetric FIR filters with boundary handling on Xilinx Virtex FPGAs. 356-359
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    Neil W. Bergmann:
    Enabling technologies for reconfigurable system-on-chip. 360-363
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    D. C. Gharpure, M. S. Puranik:
    FPGA implementation of MFNN for image registration. 364-367
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    C. Rambabu, L. Chakrabarti, Anil Mahanta:
    An efficient architecture for an improved watershed algorithm and its FPGA implementation. 370-373
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    Lei Tu, Ming-Cheng Zhu, Jing-Xia Wang:
    The hardware implementation of a genetic algorithm model with FPGA. 374-377
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    Teruyoshi Yamaguchi, Tomonori Hashiyama, Shigeru Okuma:
    Dynamic reconfiguration for the common key encryption using FPGA. 378-381
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    Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita:
    Field modifiable architecture with FPGAs and its design methodology. 382-385
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    C. H. Hsu, Trieu-Kien Truong, Ming-Haw Jing, W.-C. Wu, H. C. Wu:
    The feasibility study of designing a FPGA multiplier-core on finite field. 386-389
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    Ming-Haw Jing, C. H. Hsu, Trieu-Kien Truong, Yan-Haw Chen, Yaotsu Chang:
    The diversity study of AES on FPGA application. 390-393
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    Seyed Ghassem Miremadi, Siavash Bayat Sarmadi, Ghazanfar Asadi:
    Speedup analysis in simulation-emulation co-operation. 394-398
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    Stephen J. Melnikoff, Steven F. Quigley, Martin J. Russell:
    Performing speech recognition on multiple parallel files using continuous hidden Markov models on an FPGA. 399-402
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    Adrian Stoica, Xin Guo, Ricardo Salem Zebulum, Michael I. Ferguson, Didier Keymeulen:
    Evolution-based automated reconfiguration of field programmable analog devices. 403-406
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    Jun Jiang, Wayne Luk, Daniel Rueckert:
    FPGA-based computation of free-form deformations. 407-410
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    Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung:
    Incremental programming for reconfigurable engines. 411-415
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    Francisco Rodríguez, José Carlos Campelo, Juan José Serrano:
    Delivering error detection capabilities into a field programmable device: the HORUS processor case study. 418-421
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    Ronald Scrofano, Seonil Choi, Viktor K. Prasanna:
    Energy efficiency of FPGAs and programmable processors for matrix multiplication. 422-425
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    Christian Hinkelbein, Reinhard Männer:
    Reconfigurable hardware control software using anonymous libraries. 426-428
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    Dariusz Kania:
    Logic synthesis of multi-output functions for PAL-based CPLDs. 429-432
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    Alex Carreira, Trevor W. Fox, Laurence E. Turner:
    A method of implementing bit-serial LDI ladder filters in FPGAs using JBits. 433-436
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    Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung:
    PD-XML: extensible markup language for processor description. 437-440
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    Kara K. W. Poon, Steven J. E. Wilton:
    Sensitivity of FPGA power evaluation. 441-442
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    Ingo Fröhlich, Adrian Gabriel, Daniel Kirschner, Jörg Lehnert, Erik Lins, Markus Petri, Tiago Perez, Jim Ritman, Daniel Schäfer, Alberica Toia, Michael Traxler, Wolfgang Kuehn:
    Pattern recognition in the HADES spectrometer: an application of FPGA technology in nuclear and particle physics. 443-444
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    Yu-Tsang Chang, Yu-Te Chou, Wei-Chang Tsai, Jiann-Jenn Wang, Chen-Yi Lee:
    FPGA education and research activities in Taiwan. 445-448
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    Stephan Wong, Bastiaan Stougie, Sorin Cotofana:
    Alternatives in FPGA-based SAD implementations. 449-452
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    Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen:
    Strassen's matrix multiplication for customisable processors. 453-456

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