Hardware-Oriented Security and Trust 2015 (original) (raw)

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HOST 2015: Washington, DC, USA

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  • Efficient Implementation of Secure Systems
  • PUF
  • Posters
  • Side Channel and Fault Attacks Analysis
  • Hardware Trojan Horses, Security Analysis, Evaluations, and Metrics
  • Secure and Trusted Synthesis and Design

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  IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2015, Washington, DC, USA, 5-7 May, 2015. IEEE Computer Society 2015, ISBN 978-1-4673-7420-0

Efficient Implementation of Secure Systems

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  Aria Shahverdi, Mostafa Taha, Thomas Eisenbarth:
  Silent Simon: A threshold implementation under 100 slices. 1-6
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  Mudit Bhargava, Kaship Sheikh, Ken Mai:
  Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. 7-13
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  Kan Xiao, Domenic Forte, Mark Tehranipoor:
  Efficient and secure split manufacturing via obfuscated built-in self-authentication. 14-19

PUF

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  Georg T. Becker, Alexander Wild, Tim Güneysu:
  Security analysis of index-based syndrome coding for PUF-based key generation. 20-25
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  Pai-Yu Chen, Runchen Fang, Rui Liu, Chaitali Chakrabarti, Yu Cao, Shimeng Yu:
  Exploiting resistive cross-point array for compact design of physical unclonable function. 26-31
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  Cheng-Wei Lin, Swaroop Ghosh:
  A family of Schmitt-Trigger-based arbiter-PUFs and selective challenge-pruning for robustness and quality. 32-37

Posters

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  Meng-Day (Mandel) Yu, Matthias Hiller, Srinivas Devadas:
  Maximum-likelihood decoding of device-specific multi-bit symbols for reliable key generation. 38-43
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  Abhishek Chakraborty, Bodhisatwa Mazumdar, Debdeep Mukhopadhyay:
  A practical DPA on Grain v1 using LS-SVM. 44-47
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  Gedare Bloom, Bhagirath Narahari, Rahul Simha, Ali Namazi, Renato Levy:
  FPGA SoC architecture and runtime to prevent hardware Trojans from leaking secrets. 48-51
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  Chongxi Bao, Yang Xie, Ankur Srivastava:
  A security-aware design scheme for better hardware Trojan detection sensitivity. 52-55
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  Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar:
  Automatic obfuscated cell layout for trusted split-foundry design. 56-61
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  Lionel Rivière, Zakaria Najm, Pablo Rauzy, Jean-Luc Danger, Julien Bringer, Laurent Sauvage:
  High precision fault injections on the instruction cache of ARMv7-M architectures. 62-67
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  Zachary N. Goddard, Nicholas LaJeunesse, Thomas Eisenbarth:
  Power analysis of the t-private logic style for FPGAs. 68-71
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  Bilgiday Yuce, Nahid Farhady Ghalaty, Patrick Schaumont:
  TVVF: Estimating the vulnerability of hardware cryptosystems against timing violation attacks. 72-77
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  Athanasios Papadimitriou, Marios Tampas, David Hély, Vincent Beroulle, Paolo Maistri, Régis Leveugle:
  Validation of RTL laser fault injection model with respect to layout information. 78-81
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  Xuan Thuy Ngo, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Zakaria Najm:
  Linear complementary dual code improvement to strengthen encoded circuit against hardware Trojan horses. 82-87
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  Shamit Ghosh, Dipanwita Roy Chowdhury:
  Preventing fault attack on stream cipher using randomization. 88-91
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  Sushmita Kadiyala Rao, Deepak Krishnankutty, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
  Post-layout estimation of side-channel power supply signatures. 92-95
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  Qian Wang, An Wang, Liji Wu, Gang Qu, Guoshuang Zhang:
  Template attack on masking AES based on fault sensitivity analysis. 96-99

Side Channel and Fault Attacks Analysis

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  Dhiman Saha, Dipanwita Roy Chowdhury:
  Diagonal fault analysis of Gr⊘stl in dedicated MAC mode. 100-105
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  Richard Gilmore, Neil Hanley, Máire O'Neill:
  Neural network based attack on a masked implementation of AES. 106-111
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  Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai:
  A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. 112-117
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  Liwei Zhang, A. Adam Ding, Yunsi Fei, Pei Luo:
  Efficient 2nd-order power analysis on masked devices utilizing multiple leakage. 118-123
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  Xiaofei Guo, Naghmeh Karimi, Francesco Regazzoni, Chenglu Jin, Ramesh Karri:
  Simulation and analysis of negative-bias temperature instability aging on power analysis attacks. 124-129
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  Pascal Sasdrich, Amir Moradi, Oliver Mischke, Tim Güneysu:
  Achieving side-channel protection with dynamic logic reconfiguration on modern FPGAs. 130-136

Hardware Trojan Horses, Security Analysis, Evaluations, and Metrics

Secure and Trusted Synthesis and Design

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  Roarke Horstmeyer, Sid Assawaworrarit, Ulrich Rührmair, Changhuei Yang:
  Physically secure and fully reconfigurable data storage using optical scattering. 157-162
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  Mohammad-Mahdi Bidmeshki, Yiorgos Makris:
  Toward automatic proof generation for information flow policies in third-party hardware IP. 163-168

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