International Symposium on Physical Design 2025 (original) (raw)

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ISPD 2025: Austin, TX, USA

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  • Session 1: Opening Session and First Keynote
  • Session 3: Acceleration
  • Session 5: Emerging Technologies
  • Session 7: Retrospective and Prospective of Physical Design
  • Session 9: AI for Chip Design
  • Session 11: Cell Design
  • Session 13: Lifetime Achievement Session
  • Session 15: 3D IC Part II

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    Gracieli Posser, Stephan Held:
    Proceedings of the 2025 International Symposium on Physical Design, ISPD 2025, Austin, TX, USA, March 16-19, 2025. ACM 2025, ISBN 979-8-4007-1293-7

Session 1: Opening Session and First Keynote

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    Sachin S. Sapatnekar:
    Towards Designing and Deploying Ising Machines. 1

Session 2: Placement and DTCO

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    Anthony Agnesina, Rongjian Liang, Geraldo Pradipta, Anand Rajaram, Haoxing Ren:
    GOALPlace: Begin with the End in Mind. 2-10
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    Chung-Kuan Cheng, Byeonggon Kang, Bill Lin, Yucheng Wang:
    Invited: Scaling Standard Cell Layout Using Track Height Compression and Design Technology Co-optimization. 11-19
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    Taewhan Kim:
    Invited: Physical Design Challenges for Design Technology Co-optimization. 20-21
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    Jing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Yibo Lin, Runsheng Wang, Ru Huang:
    LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method. 22-30

Session 3: Acceleration

Session 4: Panel on Heterogenous Integration

Session 5: Emerging Technologies

Session 6: Reliability

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    Meizhi Wang, Yi-Ru Chen, S. S. Teja Nibhanupudi, Elham Amini, Antonio Saavedra, Yinan Wang, Daniel Wasserman, Jean-Pierre Seifert, Jaydeep P. Kulkarni:
    Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology. 74-82
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    Shih-Kai Lee, Pei-Yu Lee, Iris Hui-Ru Jiang:
    Multi-Stage CSM Timing Waveform Propagation Accelerated by NLDM Assistance. 83-90

Session 7: Retrospective and Prospective of Physical Design

Session 8: Second Keynote

Session 9: AI for Chip Design

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    Yuan Pu, Fangzhou Liu, Zhuolun He, Keren Zhu, Rongliang Fu, Ziyi Wang, Tsung-Yi Ho, Bei Yu:
    HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. 116-124
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    Fangzhou Liu, Guannan Guo, Yuyang Ye, Ziyi Wang, Wenjie Fu, Weihua Sheng, Bei Yu:
    GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays. 125-133
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    Qijing Wang, Liang Xiao, Evangeline F. Y. Young:
    Invited: AI-assisted Routing. 134-142

Session 10: LLM for Chip Design

Session 11: Cell Design

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    Byeonggon Kang, Ying Yuan, Yucheng Wang, Bill Lin, Chung-Kuan Cheng:
    Cell-Flex Metrics for Designing Optimal Standard Cell Layout with Enhanced Cell Layout Flexibility. 164-172
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    Ting-Wei Lee, Ting Xin Lin, Yih-Lang Li:
    Scalable CFET Cell Library Synthesis with A DRC-Aware Lookup Table to Optimize Valid Pin Access. 173-181
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    Junzhuo Zhou, Haoxuan Xia, Wei W. Xing, Ting-Jung Lin, Li Huang, Lei He:
    LVFGen: Efficient Liberty Variation Format (LVF) Generation Using Variational Analysis and Active Learning. 182-190
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    Tianjia Zhou, Cheng Chang, Li Huang, Jingyun Gu, Zexin Ji, Xiangyang Liu, Hailang Liang, Zhanfei Chen, Ting-Jung Lin, Song Wang, Na Bai, Zhengping Li, Lei He:
    Abuttable Analog Cell Library and Automatic AMS Layout. 191-199

Session 12: 3D IC Part I

Session 13: Lifetime Achievement Session

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    Bryan Preas:
    Invited: Innovation in Times of Technology Disruption. 218-219
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    David Z. Pan:
    Invited: Shaping the Future of Interconnected Physical Design. 220-221
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    Jason Cong:
    Invited: Coping with Interconnects. 222-230

Session 14: Third Keynote

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    Henry Sheng:
    Invited: Automation and Optimization of Heterogeneous Multi-Die Systems. 231-232

Session 15: 3D IC Part II

Session 16: Contest Results and Closing Remarks

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