International Symposium on Quality Electronic Design 2014 (original) (raw)

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ISQED 2014: Santa Clara, California, USA

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  • Session 1A: Memory Circuits and Systems
  • Session 1C: Network on a Chip and Multi-core Systems
  • Session 2C: Manufacturing and Modeling Issues in Nanoscale CMOS
  • Session 3B: Systems Optimization
  • Session 4A: Reliability and Aging
  • Session 4C: New Ideas in Circuit Design
  • Session 5C: Thermal and Energy Considerations in Systems

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  Fifteenth International Symposium on Quality Electronic Design, ISQED 2014, Santa Clara, CA, USA, March 3-5, 2014. IEEE 2014, ISBN 978-1-4799-3945-9
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    Jacqueline Woods, Sridhar Iyengar, Amit Sinha, Subhasish Mitra, Stacy Cannady:
    A new era of computing: Are you "ready now" to build a smarter and secured enterprise? 1

Session 1A: Memory Circuits and Systems

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    Arijit Banerjee, Mahmut E. Sinangil, John W. Poulton, C. Thomas Gray, Benton H. Calhoun:
    A reverse write assist circuit for SRAM dynamic write VMIN tracking using canary SRAMs. 1-8
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    Hu Chen, Sanghamitra Roy, Koushik Chakraborty:
    Exploiting static and dynamic locality of timing errors in robust L1 cache design. 9-15
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    Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata, Hirofumi Nakano, Makoto Yabuuchi, Hidehiro Fujiwara, Koji Nii, Hiroyuki Kawai, Hiroshi Kawaguchi, Masahiko Yoshimoto:
    A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. 16-23
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    Yoshisato Yokoyama, Yuichiro Ishii, Hidemitsu Kojima, Atsushi Miyanishi, Yoshiki Tsujihashi, Shinobu Asayama, Kazutoshi Shiba, Koji Tanaka, Tatsuya Fukuda, Koji Nii, Kazumasa Yanagisawa:
    40nm Ultra-low leakage SRAM at 170 deg.C operation for embedded flash MCU. 24-31
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    Peyman Pouyan, Esteve Amat, Enrique Barajas, Antonio Rubio:
    Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches. 32-38

Session 1B: Advanced Techniques for System-level Analysis

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    Yao Li, Ramy Iskander, Marie-Minerve Louërat:
    Modeling, design and verification platform using SystemC AMS. 39-46
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    Chongxi Bao, Domenic Forte, Ankur Srivastava:
    On application of one-class SVM to reverse engineering-based hardware Trojan detection. 47-54
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    Jarbas Silveira, Paulo César Cortez, Giovanni Cordeiro Barroso, César A. M. Marcon:
    Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation. 55-59
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    Anirban Sengupta, Vipul Kumar Mishra:
    Integrated particle swarm optimization (i-PSO): An adaptive design space exploration framework for power-performance tradeoff in architectural synthesis. 60-67
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    Saad Bin Nasir, Youngtak Lee, Arijit Raychowdhury:
    Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators. 68-75

Session 1C: Network on a Chip and Multi-core Systems

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    Tejasi Pimpalkhute, Sudeep Pasricha:
    An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors. 76-83
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    Alexandra Aguiar, Carlos Moratelli, Marcos Sartori, Fabiano Hessel:
    Adding virtualization support in MIPS 4Kc-based MPSoCs. 84-90
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    Shirish Bahirat, Sudeep Pasricha:
    HELIX: Design and synthesis of hybrid nanophotonic application-specific network-on-chip architectures. 91-98
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    Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi:
    An analytical approach to system-level variation analysis and optimization for multi-core processor. 99-106
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    Tianyi Wang, Ming Fan, Gang Quan, Shangping Ren:
    Heterogeneity exploration for peak temperature reduction on multi-core platforms. 107-114
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    Prasanjeet Das, Sandeep K. Gupta:
    Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations. 115-122
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    Syed Rameez Naqvi, Jakob Lechner, Andreas Steininger:
    Protection of Muller-Pipelines from transient faults. 123-131
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    Eduardo Wächter, Augusto Erichsen, Leonardo Juracy, Alexandre M. Amory, Fernando Moraes:
    Runtime fault recovery protocol for NoC-based MPSoCs. 132-139
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    Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Shih-Chieh Chang:
    Concurrency-oriented SoC re-certification by reusing block-level test vectors. 140-147
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    Kamran Rahmani, Prabhat Mishra, Sandip Ray:
    Efficient trace signal selection using augmentation and ILP techniques. 148-155
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    Sudhi Proch, Prabhat Mishra:
    Directed test generation for hybrid systems. 156-162

Session 2B: Package and 3-D Integration

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    Kyungsu Kang, Giovanni De Micheli, Seunghan Lee, Chong-Min Kyung:
    Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache. 163-170
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    Song Yao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang:
    Efficient region-aware P/G TSV planning for 3D ICs. 171-178
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    Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee:
    3D-ICs with self-healing capability for thermal effects in RF circuits. 179-183
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    Mir Mohammad Navidi, Gyung-Su Byun:
    Comparative analysis of clock distribution networks for TSV-based 3D IC designs. 184-188
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    Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
    Delay and power optimization with TSV-aware 3D floorplanning. 189-196
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    Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung:
    Runtime 3-D stacked cache data management for energy minimization of 3-D chip-multiprocessors. 197-204

Session 2C: Manufacturing and Modeling Issues in Nanoscale CMOS

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    Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab:
    Statistical methodology for modeling non-IID memory fails events. 205-211
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    Wei Wang:
    Automated Shmoo data analysis: A machine learning approach. 212-218
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    Seong-I Lei, Chris Chu, Wai-Kei Mak:
    Double patterning-aware detailed routing with mask usage balancing. 219-223
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    Sharayu Jagtap, Sivaramakrishna Rudrapati, Shalabh Gupta:
    Design of radiation hardened wide tuning range CMOS oscillators. 224-229
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    Tomohiro Fujita, SinNyoung Kim, Hidetoshi Onodera:
    Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model. 230-235
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    Varadan Savulimedu Veeravalli, Andreas Steininger, Ulrich Schmid:
    Measuring SET pulsewidths in logic gates using digital infrastructure. 236-242

Session 3A: Low Voltage and Low Power Design Methodologies

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    Yanqing Zhang, Benton H. Calhoun:
    Fast, accurate variation-aware path timing computation for sub-threshold circuits. 243-248
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    Xue Lin, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
    An improved logical effort model and framework applied to optimal sizing of circuits operating in multiple supply voltage regimes. 249-256
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    Bo Liu, Maryam Ashouei, Tobias Gemmeke, José Pineda de Gyvez:
    Sub-threshold custom standard cell library validation. 257-262
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    Kartikeya Bhardwaj, Pravin S. Mane, Jörg Henkel:
    Power- and area-efficient Approximate Wallace Tree Multiplier for error-resilient systems. 263-269
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    Mark Buckler, Wayne P. Burleson:
    Predictive synchronization for DVFS-enabled multi-processor systems. 270-275

Session 3B: Systems Optimization

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    Heesun Kim, Seungyun Sohn, Yoonjin Kim:
    Ring-based sharing fabric for efficient pipelining of kernel-stream on CGRA-based multi-core architecture. 276-283
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    Ming Fan, Qiushi Han, Gang Quan, Shangping Ren:
    Multi-core partitioned scheduling for fixed-priority periodic real-time tasks with enhanced RBound. 284-291
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    Parag Kulkarni, Puneet Gupta, Rudy Beraha:
    Minimizing clock domain crossing in Network on Chip interconnect. 292-299
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    Andrew B. Kahng, Siddhartha Nath:
    Optimal reliability-constrained overdrive frequency selection in multicore systems. 300-308
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    Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi:
    RTL datapath optimization using system-level transformations. 309-316
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    Anup Shrivastava, Jawar Singh:
    Dual-sided doped memristor and it's SPICE modelling for improved electrical properties. 317-322
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    Komal Singh, Chitrakant Sahu, Jawar Singh:
    Linearly separable pattern classification using memristive crossbar circuits. 323-329
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    Makoto Miyamura, Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, Koichiro Okamoto, Noriyuki Iguchi, Hiromitsu Hada:
    Low-power programmable-logic cell arrays using nonvolatile complementary atom switch. 330-334
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    Mukta Singh Parihar, Abhinav Kranti:
    Volume accumulated double gate junctionless MOSFETs for low power logic technology applications. 335-340
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    Xue Lin, Yanzhi Wang, Massoud Pedram:
    Stack sizing analysis and optimization for FinFET logic cells and circuits operating in the sub/near-threshold regime. 341-348

Poster Session and Mixer

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    Amir Momeni, Perhaad Mistry, David R. Kaeli:
    A parallel clustering algorithm for placement. 349-356
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    Chessda Uttraphan, Nasir Shaikh-Husin, Mohamed Khalil Hani:
    An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design. 357-364
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    Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
    Kriging bootstrapped neural network training for fast and accurate process variation analysis. 365-372
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    Daniela De Venuto, Peter Ledochowitsch, Michel Maharabitz, Jan M. Rabaey:
    Impedance modeling of the intracortical microelectrode for a reliable design of a brain activity recording system. 380-385
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    Ying-Chi Li, Sheldon X.-D. Tan, Tan Yu, Xin Huang, Ngai Wong:
    Direct finite-element-based solver for 3D-IC thermal analysis via H-matrix representation. 386-391
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    Yijie Huangfu, Wei Zhang:
    Compiler-directed leakage energy reduction for instruction scratch-pad memories. 392-399
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    Guilherme M. Castilhos, Eduardo Wächter, Guilherme A. Madalozzo, Augusto Erichsen, Thiago Monteiro, Fernando Moraes:
    A framework for MPSoC generation and distributed applications evaluation. 408-411
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    Varadan Savulimedu Veeravalli, Andreas Steininger:
    Architecture for monitoring SET propagation in 16-bit Sklansky adder. 412-419
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    Rafael M. Madeira, Edna Barros, Camila Ascendina:
    Towards more reliable embedded systems through a mechanism for monitoring driver devices communication. 420-427
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    Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi:
    Experimental validation of minimum operating-voltage-estimation for low supply voltage circuits. 428-433
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    Eman El Mandouh:
    Application of six-sigma DMAIC methodology in the evaluation of test effectiveness: A case study for EDA tools. 434-441
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    Hoda Pahlevanzadeh, Qiaoyan Yu:
    Systematic analyses for latching probability of single-event transients. 442-449

Session 4A: Reliability and Aging

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    Mitsuhiko Igarashi, Hideki Aono, Hideaki Abe, Koji Shibutani, Kan Takeuchi:
    Assessment of reliability impact on GHz processors with moderate overdrive. 456-460
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    Dinesh Ganta, Leyla Nazhandali:
    Study of IC aging on ring oscillator physical unclonable functions. 461-466
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    Dinesh Ganta, Leyla Nazhandali:
    Circuit-level approach to improve the temperature reliability of Bi-stable PUFs. 467-472
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    Halil Kukner, Moustafa A. Khatib, Sebastien Morrison, Pieter Weckx, Praveen Raghavan, Ben Kaczer, Francky Catthoor, Liesbet Van der Perre, Rudy Lauwereins, Guido Groeseneken:
    Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology. 473-479
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    Vikram B. Suresh, Wayne P. Burleson:
    Fine grained wearout sensing using metastability resolution time. 480-483
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    Senthil Arasu, Mehrdad Nourani, Frank Cano, John M. Carulli, Vijay Reddy:
    Asymmetric aging of clock networks in power efficient designs. 484-486

Session 4B: Advances in Timing Closure and Yield/Reliability Improvement

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    Sandeep Shambhulingaiah, Srivatsan Chellappa, Sushil Kumar, Lawrence T. Clark:
    Methodology to optimize critical node separation in hardened flip-flops. 486-490
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    Hyungjung Seo, Taewhan Kim:
    Post-silicon tunable clock buffer allocation based on fast chip yield computation. 490-495
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    Andrew B. Kahng, Hyein Lee:
    Timing margin recovery with flexible flip-flop timing model. 496-503
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    Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li:
    NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation. 504-509

Session 4C: New Ideas in Circuit Design

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    Sandeep Koranne:
    Constructing small-signal equivalent impedances using ellipsoidal norms. 510-516
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    Mehrdad Khatir, Leyla Nazhandali:
    Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit. 517-522
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    Hidehiro Fujiwara, Makoto Yabuuchi, Koji Nii:
    Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS. 523-528
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    Sung S.-Y. Hsueh, Ryan H.-M. Huang, Charles H.-P. Wen:
    TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits. 529-534
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    Santhosh Kumar Rethinagiri, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Rabie Ben Atitallah, Smaïl Niar:
    PETS: Power and energy estimation tool at system-level. 535-542
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    Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi:
    Impact of FinFET technology for power gating in nano-scale design. 543-547
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    Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
    Avoiding unnecessary write operations in STT-MRAM for low power implementation. 548-553
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    Chao Sun, Ayumi Soga, Takahiro Onagi, Koh Johguchi, Ken Takeuchi:
    A workload-aware-design of 3D-NAND flash memory for enterprise SSDs. 554-561
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    Md. Abir Khan, Saraju P. Mohanty, Elias Kougianos:
    Statistical process variation analysis of a graphene FET based LC-VCO for WLAN applications. 569-574
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    Tiansong Cui, Shuang Chen, Yanzhi Wang, Shahin Nazarian, Massoud Pedram:
    An efficient semi-analytical current source model for FinFET devices in near/sub-threshold regime considering multiple input switching and stack effect. 575-581

Session 5B: Assertion and Formal Verification Technologies

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    Hasan Sohofi, Zainalabedin Navabi:
    Assertion-based verification for system-level designs. 582-588
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    Binghao Bao, Jörg Bormann, Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
    Coverage of compositional property sets under reactive constraints. 589-596
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    Kai-Hui Chang, Yen-Ting Liu, Chris Browy:
    Automated methods for eliminating X bugs. 597-603
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    Amir Masoud Gharehbaghi, Masahiro Fujita:
    Specification and formal verification of power gating in processors. 604-610
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    Miroslav N. Velev, Ping Gao:
    Formal verification of safety of polymorphic heterogeneous multi-core architectures. 611-617
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    Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le:
    Simulation and satisfiability guided counter-example triage for RTL design debugging. 618-624

Session 5C: Thermal and Energy Considerations in Systems

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    Darshan Gandhi, Andreas Gerstlauer, Lizy K. John:
    FastSpot: Host-compiled thermal estimation for early design space exploration. 625-632
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    Abhishek A. Sinkar, Hao Wang, Nam Sung Kim:
    Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores. 633-638
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    Ping Chi, Cong Xu, Xiaochun Zhu, Yuan Xie:
    Building energy-efficient multi-level cell STT-MRAM based cache through dynamic data-resistance encoding. 639-644
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    Jacob Murray, Paul Wettin, Ryan Gary Kim, Xinmin Yu, Partha Pratim Pande, Behrooz A. Shirazi, Deuk Hyoun Heo:
    Thermal hotspot reduction in mm-Wave wireless NoC architectures. 645-652
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    Florin Balasa, Noha Abuaesh, Cristian V. Gingu, Ilie I. Luican, Doru V. Nasui:
    Energy-aware scratch-pad memory partitioning for embedded systems. 653-659
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    Ying Zhang, Lide Duan, Bin Li, Lu Peng, Sadagopan Srinivasan:
    Energy efficient job scheduling in single-ISA heterogeneous chip-multiprocessors. 660-666

Session 6A: Advanced Circuit and System Methodologies

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    Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar:
    ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes. 667-674
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    Majid Jalalifar, Gyung-Su Byun:
    An energy-efficient mobile PAM memory interface for future 3D stacked mobile DRAMs. 675-680
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    Ting Chen, Xiaowei Pan, Hengzhu Liu, Tiebin Wu:
    Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0. 681-687
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    Matheus T. Moreira, Julian J. H. Pontes, Ney Laert Vilar Calazans:
    Tradeoffs between RTO and RTZ in WCHB QDI asynchronous design. 692-699
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    Zhong Guan, Malgorzata Marek-Sadowska, Sani R. Nassif:
    Statistical analysis of process variation induced SRAM electromigration degradation. 700-707
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    Di-An Li, Malgorzata Marek-Sadowska:
    Estimating true worst currents for power grid electromigration analysis. 708-714
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    Le Zhang, Vivek Sarin:
    An enlarged-partition based preconditioned iterative solver for parallel power grid simulation. 715-722
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    Konstantis Daloukas, Nestor E. Evmorfopoulos, Panagiota E. Tsompanopoulou, George I. Stamoulis:
    A 3-D Fast Transform-based preconditioner for large-scale power grid analysis on massively parallel architectures. 723-730
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    Arunkumar Vijayakumar, Vinay C. Patil, Girish Paladugu, Sandip Kundu:
    On pattern generation for maximizing IR drop. 731-737
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    Yucai Wang, Vamsy P. Chodavarapu:
    Design of a CMOS readout circuit for wide-temperature range capacitive MEMS sensors. 738-742
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    Harald Steiner, Wilfried Hortschitz, Franz Keplinger, Thilo Sauter:
    Topology optimization of a passive thermal actuator. 743-747
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    Thilo Sauter, Thomas Glatzl, Franz Kohl, Harald Steiner, Almir Talic:
    Thermal flow sensors based on printed circuit board technology. 748-753
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    Sachin Agrawal, Sunil Kumar Pandey, Jawar Singh, Manoj Singh Parihar:
    Realization of efficient RF energy harvesting circuits employing different matching technique. 754-761
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    Jiyuan Luan, Michael DiVita:
    An integrated precision clock generator for implanted electronics with superior long-term stability. 762-765

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