Annual Symposium on VLSI 2003 (original) (raw)

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ISVLSI 2003: Tampa, Florida, USA

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  2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA. IEEE Computer Society 2003, ISBN 0-7695-1904-0

Full Papers

Emerging Trends in VLSI Systems

• 
  Justin E. Harlow III:
  Toward Design Technology in 2020: Trends, Issues, and Challenges. 3-4
• 
  José A. B. Fortes:
  Future Challenges in VLSI Design. 5-7
• 
  Radu Marculescu:
  Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. 8-12
• 
  Shamik Das, Anantha P. Chandrakasan, Rafael Reif:
  Three-Dimensional Integrated Circuits: Performance, Design Methodology, and CAD Tools. 13-18
• 
  Sarah E. Frost, Arun Rodrigues, Charles A. Giefer, Peter M. Kogge:
  Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory. 19-28

Advanced VLSI Design

• 
  Koushik K. Das, Richard B. Brown:
  Novel Circuit Styles for Minimization of Floating Body Effects in Scaled PD-SOI CMOS. 29-34
• 
  Edward Malley, Ariel Salinas, Kareem Ismail, Lawrence T. Pileggi:
  Power Comparison of Throughput Optimized IC Busses. 35-44
• 
  Yonghee Im, Kaushik Roy:
  LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits. 45-54

VLSI Circuits and Systems

• 
  Srividya Srinivasaraghavan, Wayne P. Burleson:
  Interconnect Effort - A Unification of Repeater Insertion and Logical Effort. 55-61
• 
  Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra:
  Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design. 62-69
• 
  Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
  A Fine-Grain Phased Logic CPU. 70-79
• 
  Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang:
  An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. 80-86

System-on-a-Chip Design

• 
  Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
  Energy Benefits of a Configurable Line Size Cache for Embedded Systems. 87-91
• 
  S. Kagan Agun, J. Morris Chang:
  Reconfigurable Fast Memory Management System Design for Application Specific Processors. 92-100

System Level Design

• 
  Jolin M. Warren, Thomas L. Martin, Asim Smailagic, Daniel P. Siewiorek:
  System Design Approach To Power Aware Mobile Computers. 101-106
• 
  Jürgen Becker, Martin Vorbach:
  Architecture, Memory and Interface Technology Integration of an Industrial/Academic Configurable System-on-Chip (CSoC). 107-112
• 
  Catherine H. Gebotys, Robert J. Gebotys:
  A Framework for Security on NoC Technologies. 113-120

Low Power VLSI System Design I

• 
  Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
  Peak Power Minimization Through Datapath Scheduling. 121-126
• 
  Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir:
  Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. 127-132
• 
  Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou:
  Energy Recovering ASIC Design. 133-138
• 
  Yu Bai, R. Iris Bahar:
  A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. 139-148

Low Power VLSI System Design II

• 
  Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw:
  An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages. 149-154
• 
  Maciej Bellos, Dimitri Kagaris, Dimitris Nikolos:
  Low Power Test Set Embedding Based on Phase Shifters. 155-160
• 
  W. Kuang, J. S. Yuan, Abdel Ejnioui:
  Supply Voltage Scalable System Design Using Self-Timed Circuits. 161-166
• 
  Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif:
  Optimal shielding/spacing metrics for low power design. 167-172
• 
  Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee:
  An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs. 173-182

Physical Design, Synthesis and Optimization

• 
  Andrew B. Kahng, Bao Liu:
  Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization. 183-188
• 
  Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi:
  Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies. 189-192
• 
  Tapani Ahonen, Tero Nurmi, Jari Nurmi, Jouni Isoaho:
  Block-wise Extraction of Rent's Exponents for an Extensible Processor. 193-202

Poster Papers

• 
  Sumeer Goel, Tarek Darwish, Magdy A. Bayoumi:
  A Novel Technique for Noise-Tolerance in Dynamic Circuits. 203-206
• 
  Shang Xue, Bengt Oelmann:
  Efficient VLSI Implementation of a VLC Decoder for Universal Variable Length Code. 207-208
• 
  Hanho Lee:
  An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. 209-210
• 
  Chandramouli Gopalakrishnan, Srinivas Katkoori:
  An Architectural Leakage Power Simulator for VHDL Structural Datapaths. 211-212
• 
  Ming-Jung Seow, Hau T. Ngo, Vijayan K. Asari:
  Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association. 213-214
• 
  Satish Ravichandran, Vijayan K. Asari:
  Pre-computatio of Rotatio Bits in Unidirectional CORDIC for Trigonometric and Hyperbolic Computations. 215-216
• 
  Jung-Lin Yang, Erik Brunvand:
  Self-Timed Design with Dynamic Domino Circuits. 217-219
• 
  Jiangjiang Liu, Nihar R. Mahapatra, Krishnan Sundaresan:
  Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses. 220-221
• 
  Marc Leeman, Chantal Ykman-Couvreur, David Atienza, Vincenzo De Florio, Geert Deconinck:
  Automated Dynamic Memory Data Type Implementation Exploration and Optimization. 222-224
• 
  Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson, Lars J. Svensson:
  Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. 225-230
• 
  Andrea Lodi, Luca Ciccarelli, Andrea Cappelli, Fabio Campi, Mario Toma:
  Decoder-Based Multi-Context Interconnect Architecture. 231-233
• 
  Ioannis Papaefstathiou:
  Titan II : An IPComp Processor for 10Gbit/sec networks. 234-235
• 
  Hyung-Jin Lee, Dong Sam Ha:
  Frequency Domain Approach for CMOS Ultra-Wideband Radios. 236-237
• 
  W. Rhett Davis:
  Getting High-Performance Silicon from System-Level Design. 238-243
• 
  Bassam Shaer, Kailash Aurangabadkar, Nitin Agarwal:
  Testable Sequential Circuit Design: Partitioning for Pseudoexhaustive Test. 244-245
• 
  Shalini Ghosh, Sugato Basu, Nur A. Touba:
  Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering. 246-249
• 
  Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii:
  Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization. 250-251
• 
  M. Madhu, V. Srinivasa Murty, V. Kamakoti:
  Dynamic Coding Technique For Low-Power Data Bus. 252-253
• 
  Hongping Li, John K. Antonio, Sudarshan K. Dhall:
  Fast and Precise Power Prediction for Combinational Circuits. 254-259
• 
  Jia Di, Jiann-Shiun Yuan, Ronald F. DeMara:
  High Throughput Power-Aware FIR Filter Design Based on Fine-Grain Pipelining Multipliers and Adders. 260-261
• 
  Krishnan Sundaresan, Nihar R. Mahapatra:
  Code Compression Techniques for Embedded Systems and Their Effectiveness. 262-263
• 
  Sandeep K. Kondapuram, Peter M. Maurer:
  Random Characterization of Design Automation Algorithms. 264-265
• 
  Hua Tang, Hui Zhang, Alex Doboli:
  Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing. 266-271
• 
  Jihong Ren, Mark R. Greenstreet:
  Equalizing Filter Design for Crosstalk Cancellation. 272-274
• 
  Jan Lundgren, Bengt Oelmann, Trond Ytterdal, Patrik Eriksson, Munir Abdalla, Mattias O'Nils:
  Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC. 275-277
• 
  Li Yang, J. S. Yuan:
  Enhanced Techniques for Current Balanced Logic in Mixed-Signal ICs. 278-279
• 
  Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi:
  Quantum Voltage Comparator for 0.07 mum CMOS Flash A/D Converters. 280-282

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