Annual Symposium on VLSI 2012 (original) (raw)

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ISVLSI 2012: Amherst, MA, USA

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  • Ph.D. Forum
  • Thermal Analysis and 3D IC Design
  • RRAM and Computing
  • Advanced Circuit Design Techniques
  • Hardware Security
  • Reversible Design Technologies
  • Design Architecture
  • Methodology for Efficient Multi-threading of Parsers in Electronic Design Automation Tools
  • Design Modeling and Analysis
  • System Innovations with Emerging Memory Technologies

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  IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, Amherst, MA, USA, August 19-21, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-2234-8

Ph.D. Forum

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  Youngsoo Kim, Winser E. Alexander, William W. Edmonson:
  A Dataflow Framework for DSP Algorithm Refinement. 1-2
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  Daniel B. Limbrick:
  Impact of Logic Synthesis on Soft Error Rate of Digital Integrated Circuits. 3-4
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  Himanshu Thapliyal, Nagarajan Ranganathan:
  Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. 5-6
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  Sudip Roy, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya:
  Algorithms for On-Chip Solution Preparation Using Digital Microfluidic Biochips. 7-8

NoC/Router Design

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  Maryam Bahmani, Abbas Sheibanyrad, Frédéric Pétrot, Florentine Dubois, Paolo Durante:
  A 3D-NoC Router Implementation Exploiting Vertically-Partially-Connected Topologies. 9-14
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  Vinitha Arakkonam Palaniveloo, Arcot Sowmya:
  Formal Estimation of Worst-Case Communication Latency in a Network-on-Chip. 15-20
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  Marios Evripidou, Chrysostomos Nicopoulos, Vassos Soteriou, Jongman Kim:
  Virtualizing Virtual Channels for Increased Network-on-Chip Robustness and Upgradeability. 21-26
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  Infall Syafalni, Tsutomu Sasao:
  A Fast Head-Tail Expression Generator for TCAM - Application to Packet Classification. 27-32

Thermal Analysis and 3D IC Design

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  Bing Shi, Ankur Srivastava, Avram Bar-Cohen:
  Hybrid 3D-IC Cooling System Using Micro-fluidic Cooling and Thermal TSVs. 33-38
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  Eric Guthmuller, Ivan Miro Panades, Alain Greiner:
  Adaptive Stackable 3D Cache Architecture for Manycores. 39-44
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  Kunal P. Ganeshpure, Sandip Kundu:
  Reducing Temperature Variation in 3D Integrated Circuits Using Heat Pipes. 45-50
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  Simone Corbetta, Davide Zoni, William Fornaciari:
  A Temperature and Reliability Oriented Simulation Framework for Multi-core Architectures. 51-56

VLSI Architectures, Designs, and Implementations of Cryptographic Systems for Constrained Resources Environments

RRAM and Computing

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  Rashmi Jha, Branden Long:
  Understanding the Switching Mechanism in Transition Metal Oxide Based ReRAM Devices. 73-77
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  Azer Faraclas, Nicholas E. Williams, Faruk Dirisaglik, Kadir Cil, Ali Gokirmak, Helena Silva:
  Operation Dynamics in Phase-Change Memory Cells and the Role of Access Devices. 78-83
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  Jeyavijayan Rajendran, Garrett S. Rose, Ramesh Karri, Miodrag Potkonjak:
  Nano-PPUF: A Memristor-Based Security Primitive. 84-87
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  Ganesh Khedkar, Dhireesha Kudithipudi:
  RRAM Motifs for Mitigating Differential Power Analysis Attacks (DPA). 88-93

Logic Synthesis and Testing

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  Maciej Nikodem, Marek A. Bawiec, Janusz Biernat:
  Synthesis of Multithreshold Threshold Gates. 94-99
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  Yingying Zhang, Emmanuel Rodriguez, Hao Zheng, Chris J. Myers:
  An Improvement in Partial Order Reduction Using Behavioral Analysis. 100-107
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  Kunal P. Ganeshpure, Sandip Kundu:
  A DFT Methodology for Repairing Embedded Memories of Large MPSoCs. 108-113
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  Sanga Chaki, Chandan Giri, Hafizur Rahaman:
  Binary Difference Based Test Data Compression for NoC Based SoCs. 114-119

Advanced Circuit Design Techniques

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  Arunkumar Vijayakumar, Raghavan Kumar, Sandip Kundu:
  On Design of Low Cost Power Supply Noise Detection Sensor for Microprocessors. 120-125
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  Trivikrama Rao, Ashudeb Dutta, Shiv Govind Singh, Arijit De, Bhibu Dutta Sahoo:
  A Tuneable CMOS Pulse Generator for Detecting the Cracks in Concrete Walls. 126-130
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  Xuelian Liu, John F. McDonald:
  A Wide Band Locking Range Quarter-PhaseGenerator PLL Using 0.13um BiCMOS Technology. 131-134

Emerging Circuit Technologies

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  Amlan Chakrabarti, Chia-Chun Lin, Niraj K. Jha:
  Design of Quantum Circuits for Random Walk Algorithms. 135-140
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  Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty:
  An Investigation of Concurrent Error Detection over Binary Galois Fields in CNTFET and QCA Technologies. 141-146
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  Mohsen M. Arjmand, Mohsen Soryani, Keivan Navi, Mohammad A. Tehrani:
  A Novel Ternary-to-Binary Converter in Quantum-Dot Cellular Automata. 147-152
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  Ravindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan:
  Ultra Low Power Circuit Design Using Tunnel FETs. 153-158

Hardware Security

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  Apostolos P. Fournaris, Odysseas G. Koufopavlou:
  Protecting CRT RSA against Fault and Power Side Channel Attacks. 159-164
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  Raghavan Kumar, Vinay C. Patil, Sandip Kundu:
  On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators. 165-170
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  Domenic Forte, Ankur Srivastava:
  Manipulating Manufacturing Variations for Better Silicon-Based Physically Unclonable Functions. 171-176
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  Yuejian Fang, Zhonghai Wu:
  A New Parallel Processor Architecture for Genus 2 Hyperelliptic Curve Cryptosystems. 177-182

Reliability and Fault Tolerance

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  Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang:
  Temporal Performance Degradation under RTN: Evaluation and Mitigation for Nanoscale Circuits. 183-188
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  Rishad A. Shafik, Bashir M. Al-Hashimi, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
  RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework. 189-194
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  Tao Jin, Shuai Wang:
  Aging-Aware Instruction Cache Design by Duty Cycle Balancing. 195-200

Reversible Design Technologies

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  Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
  Design of Prefix-Based Optimal Reversible Comparator. 201-206
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  Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan:
  Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. 207-212
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  Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler:
  Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. 213-218
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  Matthew Morrison, Nagarajan Ranganathan:
  Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. 219-224

Datapath Design and Partitioning

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  Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
  Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. 225-230
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  Matthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan:
  Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. 231-236
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  Tung Thanh Hoang, Per Larsson-Edefors:
  Data-Width-Driven Power Gating of Integer Arithmetic Circuits. 237-242
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  Yu Jiang, Hehua Zhang, Xun Jiao, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun:
  Uncertain Model and Algorithm for Hardware/Software Partitioning. 243-248

Design Architecture

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  Oliver Arnold, Benedikt Noethen, Gerhard P. Fettweis:
  Instruction Set Architecture Extensions for a Dynamic Task Scheduling Unit. 249-254
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  Nagarajan Venkateswaran, Rajagopal Hariharan, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Vigneshwaran Sankaran, Bharanidharan Vasudevan, Ravindhiran Mukundrajan, Nachiappan Chidambaram Nachiappan, Aswin Sridharan, Karthikeyan P. Saravanan, Vignesh Adhinarayanan, Vignesh Veppur Sankaranarayanan:
  SCOC IP Cores for Custom Built Supercomputing Nodes. 255-260
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  Marco Aurelio Nuño-Maganda, Miguel O. Arias-Estrada, César Torres-Huitzil, Héctor Hugo Avilés-Arriaga, Yahir Hernández-Mier, Miguel Morales-Sandoval:
  A Hardware Architecture for Image Clustering Using Spiking Neural Networks. 261-266
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  Nagarajan Venkateswaran, Vinesh Srinivasan, Ram Srivatsa Kannan, Prashanth Thinakaran, Rajagopal Hariharan, Bharanidharan Vasudevan, Nachiappan Chidambaram Nachiappan, Karthikeyan P. Saravanan, Aswin Sridharan, Vigneshwaran Sankaran, Vignesh Adhinarayanan, V. S. Vignesh, Ravindhiran Mukundrajan:
  Compilation Accelerator on Silicon. 267-272

Analog Design

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  Geng Zheng, Saraju P. Mohanty, Elias Kougianos:
  Metamodel-Assisted Fast and Accurate Optimization of an OP-AMP for Biomedical Applications. 273-278
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  Arnab Khawas, Siddhartha Mukhopadhyay:
  Variance Optimization of CMOS OpAmp Performances Using Experimental Design Approach. 279-284
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  Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov, Geng Zheng:
  Stochastic Gradient Descent Optimization for Low Power Nano-CMOS Thermal Sensor Design. 285-290

Methodology for Efficient Multi-threading of Parsers in Electronic Design Automation Tools

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  Prakash Shanbhag, Chandramouli Gopalakrishnan, Saibal Ghosh:
  Methodology for Efficient Multi-threading of Parsers in EDA Tools. 291-296
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  Prakash Shanbhag, Chandramouli Gopalakrishnan, Saibal Ghosh:
  A Case Study in Developing an Efficient Multi-threaded EDA Parser: Synopsys SDF Parser. 297-301

Design Fabric and Microfluidic Design

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  Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki:
  Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs. 302-307
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  Takahiro Watanabe, Minoru Watanabe:
  0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. 308-313
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  Debasis Mitra, Sudip Roy, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
  On-Chip Sample Preparation with Multiple Dilutions Using Digital Microfluidics. 314-319
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  Pranab Roy, Rupam Bhattacharjee, Hafizur Rahaman, Parthasarathi Dasgupta:
  A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips. 320-325

Design Modeling and Analysis

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  Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos:
  Geostatistical-Inspired Metamodeling and Optimization of Nano-CMOS Circuits. 326-331
• 
  John Lee, Puneet Gupta, Fedor Pikus:
  Parametric Hierarchy Recovery in Layout Extracted Netlists. 332-337
• 
  Raul Chipana, Eduardo Chielle, Fernanda Lima Kastensmidt, Jorge L. Tonfat, Ricardo Reis:
  Soft-Error Probability Due to SET in Clock Tree Networks. 338-343
• 
  Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas:
  Delay Analysis for an N-Input Current Mode Threshold Logic Gate. 344-349

New Techniques for Secure Embedded Systems

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  Ashok Srivastava, Rajiv Soundararajan:
  Testing of Trusted CMOS Data Converters. 350-355
• 
  Pei-Wen Luo, Tao Wang, Chin-Long Wey, Liang-Chia Cheng, Bih-Lan Sheu, Yiyu Shi:
  Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs). 356-361
• 
  Mahadevan Gomathisankaran, Akhilesh Tyagi:
  A Novel Design of Secure and Private Circuits. 362-367
• 
  Arun K. Kanuparthi, Ramesh Karri, Gaston Ormazabal, Sateesh Addepalli:
  A Survey of Microarchitecture Support for Embedded Processor Security. 368-373

System Innovations with Emerging Memory Technologies

Hardware-Software Co-design for Emerging Nonvolatile Memory

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