dblp: SLIP 2004 (original) (raw)

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6th SLIP 2004: Paris, France

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  • Interconnect analysis for SoCs and microprocessors
  • Models and metrics of interconnect performance
  • Interconnect design and optimization
  • Interconnect in communication networks
  • Unconventional interconnects
  • Statistical interconnect prediction

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• > Home > Conferences and Workshops > SLIP

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    Louis Scheffer, Igor L. Markov:
    The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings. ACM 2004, ISBN 1-58113-818-0

Interconnect analysis for SoCs and microprocessors

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    Reinaldo A. Bergamaschi:
    Early and accurate analysis of SoCs: oxymoron or real? 3-6
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    Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir:
    Interconnect-power dissipation in a microprocessor. 7-13

Models and metrics of interconnect performance

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    Bipin Rajendran, Pawan Kapur, Krishna Saraswat, R. Fabian W. Pease:
    Self-consistent power/performance/reliability analysis for copper interconnects. 17-22
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    Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
    Investigation of performance metrics for interconnect stack architectures. 23-29
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    Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li:
    Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. 31-38

Interconnect design and optimization

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    Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex:
    Interconnect width selection for deep submicron designs using the table lookup method. 41-44
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    Vikas Chandra, Anthony Xu, Herman Schmit:
    A low power approach to system level pipelined interconnect design. 45-52
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    Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi:
    Topology optimization for application-specific networks-on-chip. 53-60

Interconnect in communication networks

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    Dmitri B. Chklovskii:
    Evolution as the blind engineer: wiring minimization in the brain. 63
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    Ajay Joshi, Jeffrey A. Davis:
    A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). 64-68
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    Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson:
    NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. 69-75

Unconventional interconnects

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    Ian O'Connor:
    Optical solutions for system-level interconnect. 79-88
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    Arvind Kumar, Sandip Tiwari:
    Defect tolerance for nanocomputer architecture. 89-96

Statistical interconnect prediction

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    Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix:
    Prediction of interconnect adjacency distribution: derivation, validation, and applications. 99-106
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    Tao Wan, Malgorzata Chrzanowska-Jeske:
    Prediction of interconnect net-degree distribution based on Rent's rule. 107-114
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    Maurizio Martina, Guido Masera:
    A statistical model for estimating the effect of process variations on crosstalk noise. 115-120

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