IEEE International SoC Conference 2009 (original) (raw)

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SoCC 2009: Belfast, Northern Ireland, UK

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  • Plenary Session
  • Session WA2 - PLL and Clocks
  • Session WB1 - A/D Converters
  • Session WB3 - Low-Power Circuits and Architectures
  • Session TA2 - NoC Power and Data Flow Optimization
  • Poster Session
  • Session TB2 - System Level Design for Manufacturing
  • Session FA1 - Low-Power Design Methodologies and IP Cores
  • Session FB1 - System Level Architecture Exploration
  • Tutorials

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  Annual IEEE International SoC Conference, SoCC 2009, September 9-11, 2009, Belfast, Northern Ireland, UK, Proceedings. IEEE 2009, ISBN 978-1-4244-4940-8

Plenary Session

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    Hermann Eul:
    Keynote speaker. 3-4
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    James O'Riordan:
    Plenary presentation A. 5
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    Liang-Gee Chen:
    Plenary presentation B. 6

Session WA1: FPGA Design Methodologies

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    Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William George Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong:
    A high-level compilation toolchain for heterogeneous systems. 9-18
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    Maurizio Tranchero, Leonardo Maria Reyneri:
    A multi-level simulation approach in a Simulink-based design tool for FPGAs. 19-22
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    Joseph M. Lancaster, Jeremy D. Buhler, Roger D. Chamberlain:
    Efficient runtime performance monitoring of FPGA-based applications. 23-28
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    Süleyman Sirri Demirsoy, Kellie Marks:
    SoC framework for FPGA: A case study of LTE PUSCH receiver. 29-32

Session WA2 - PLL and Clocks

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    Saiyu Ren, Ray Siferd:
    Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS. 35-38
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    Ping Lu, Danfeng Chen, Fan Ye, Junyan Ren:
    A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator. 39-42
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    Nan Xing, Heesoo Song, Deog-Kyoon Jeong, Suhwan Kim:
    A PVT-insensitive time-to-digital converter using fractional difference Vernier delay lines. 43-46
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    Marta Blaszczyk, Richard A. Guinee:
    Hardware implementation on PCB in tandem with FPGA and experimental validation of a novel true random binary generator. 47-50
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    Chorng-Sii Hwang, Chun-Yung Cho, Chung-Chun Chen, Hen-Wai Tsao:
    Dual-band CDR using a half-rate linear phase detector. 51-54

Session WA3 - Reconfigurable Architectures

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    Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan:
    A novel high-efficiency partial-parallel context modeling architecture for EBCOT in JPEG2000. 57-60
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    Chun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee:
    Tuning instruction customisation for reconfigurable system-on-chip. 61-64
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    Mahtab Niknahad, Michael Hübner, Jürgen Becker:
    Method for improving performance in online routing of reconfigurable nano architectures. 65-68

Session WB1 - A/D Converters

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    Yan Wang, Gabor C. Temes:
    Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder. 71-74
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    Dongheon Lee, Seunghun Kim, Jooho Hwang, Junho Moon, Minkyu Song:
    Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique. 79-82
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    Manho Kim, Nan Xing, Dong-Yong Shin, Hyunjoong Lee, Suhwan Kim:
    A high resolution capacitance deviation-to-digital converter utilizing time stretching. 83-86

Session WB2 - Embedded Systems, Multi Core, and Embedded Memory

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    Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
    Adaptive energy-aware latency-constrained DVFS policy for MPSoC. 89-92
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    Vassilios A. Chouliaras, Konstantinos Manolopoulos, Dionysios I. Reisis:
    A configurable length, Fused Multiply-Add floating point unit for a VLIW processor. 93-96
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    Wei Han, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan:
    Heterogeneous multi-core architectures with dynamically reconfigurable processors for WiMAX transmitter. 97-100
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    Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
    Asymmetrical Write-assist for single-ended SRAM operation. 101-104

Session WB3 - Low-Power Circuits and Architectures

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    Abhinav Kranti, G. Alastair Armstrong:
    Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs. 107-110
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    Björn Lipka, Ulrich Kleine, Christoph Scheytt, Klaus Schmalz:
    Design of a complementary folded-cascode operational amplifier. 111-114
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    Yi-Ming Chang, Ming-Hung Chang, Wei Hwang:
    A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. 115-118
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    Tung Thanh Hoang, Magnus Själander, Per Larsson-Edefors:
    High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. 119-122

Session TA1 - Circuits for RF and Wireless

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    Vincent F. Fusco, Chuang Wang:
    54-65 GHz six port demodulator. 125-128
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    Vincent F. Fusco, Chuang Wang:
    Ultra wideband 32-67GHz phase shift keyed modulator. 129-132
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    Tero Koivisto, Esa Tiiliharju:
    A linearized low-voltage oscillator-mixer. 133-136
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    Kai Xuan, Kim Fung Tsang, Shu Chuen Lee, Wah Ching Lee:
    A current bleeding mixer based on Gilbert-cell featuring LO amplification. 137-140

Session TA2 - NoC Power and Data Flow Optimization

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    Simon J. Hollis, Chris Jackson:
    When does Network-on-Chip bypassing make sense? 143-146
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    G. Vikas, Joy Kuri, Kuruvilla Varghese:
    Power optimal Network-on-Chip interconnect design. 147-150
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    Zhonghai Lu, Dimitris Brachos, Axel Jantsch:
    A flow regulator for On-Chip Communication. 151-154
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    Mohamed A. Abd El-Ghany, Magdy A. El-Moursy, Mohammed Ismail:
    High throughput architecture for CLICHÉ Network on Chip. 155-158

Session TA3 - Design for Testability and Verification

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    Kuen-Jong Lee, Si-Yuan Liang, Alan P. Su:
    A low-cost SOC debug platform based on on-chip test architectures. 161-164
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    Cristian E. Onete:
    Comparator testing in a flash A/D converter. 165-168
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    Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann:
    A prototype platform for system-on-chip ADC test and measurement. 169-172
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    Mariagrazia Graziano, Marco Diego Vittori:
    A fully digital power supply noise thermometer. 173-176

Poster Session

Analog and Mixed Signals

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    Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang:
    A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS. 179-182
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    Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas:
    A novel low power, variable resolution pipelined ADC. 183-186
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    P. Srinivasan, Andrew Marshall:
    Correlating op-amp circuit noise with device flicker (1/f) noise for analog design applications. 191-194

RF and Wireless

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    Marc Molina, Xavier Aragonès, José Luis González:
    Experimental analysis of substrate isolation techniques for RF-SOC integration. 199-202
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    Chuang Wang, Vincent F. Fusco:
    High-purity 56-66GHz quadrupler for V-band radio homodyne and heterodyne transceiver applications. 203-205

Embedded Systems, Multi Core, and Embedded Memory

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    Jui-Chieh Lin, Minja Hsieh, Ming-Jung Fan-Chiang, Chu Yu, Sao-Jie Chen, Yu Hen Hu:
    An instruction set architecture independent design method for embedded OFDM-based software defined transmitter. 207-210
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    Robert J. Ascott, Earl E. Swartzlander Jr.:
    JavaFlow - A Java dataflow machine. 211-214
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    Chander Sudanthi, Mrinmoy Ghosh, Kevin Welton, Nigel C. Paver:
    Performance analysis of compressed instruction sets on workloads targeted at mobile internet devices. 215-218

Low Power

Verification

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    Younsun Kim, Hong-Sik Kim, R. Lee, Sungho Kang:
    FPGA-based verification methodology of SoC-type CMOS image signal processor. 231-234

Audio and Video Processing

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    Hui Geng, Weiqian Liang, Ming Dong:
    A speech recognition SoC based on ARM7-TDMI core and a MSAC co-processor. 235-238
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    Chun F. Hsu, Mong-Kai Ku, Li-Yen Liu:
    Support vector machine FPGA implementation for video shot boundary detection application. 239-242

Network on Chip and Interconnect

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    Shufan Yang, Stephen B. Furber, Luis A. Plana:
    Adaptive admission control on the SpiNNaker MPSoC. 243-246
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    Alexander Fell, Prasenjit Biswas, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
    Generic routing rules and a scalable access enhancement for the Network-on-Chip RECONNECT. 251-254
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    Xiaofei Guo, Shunting Lin, Wael Refai, Garrett S. Rose:
    Non-overlapping transition encoding for global on-chip interconnect. 255-258
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    Azeez Sanusi, Magdy A. Bayoumi:
    Smart-flooding: A novel scheme for fault-tolerant NoCs. 259-262

System Level Design Methodology

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    Philipp A. Hartmann, Philipp Reinkemeier, Achim Rettberg, Wolfgang Nebel:
    Modelling control systems in SystemC AMS - Benefits and limitations. 263-266
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    Yang Sun, Joseph R. Cavallaro, Tai Ly:
    Scalable and low power LDPC decoder design using high level algorithmic synthesis. 267-270

Reconfigurable and Programmable Circuits and Systems, FPGAs

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    Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel:
    A versatile fading simulator for on-chip verification of MIMO communication systems. 271-274
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    Ahmed O. El-Rayis, Xin Zhao, Tughrul Arslan, Ahmet T. Erdogan:
    Low power RS codec using cell-based reconfigurable processor. 279-282
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    Arfan Ghani, Liam McDaid, Ammar Belatreche, Waqar Ahmed:
    Neuro inspired reconfigurable architecture for hardware/software co-design. 287-290

NEMS/MEMS Devices

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    Ryoko Hayashi, Vijay K. Jain:
    Capacitance change estimation for an immunosensor chip. 291-294
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    Ambarish Roy, Bradley P. Barber, Kanti Prasad:
    RF-MEMS resonator design for parameter characterization. 295-298

Session TB1 - Analog Circuit Techniques

Session TB2 - System Level Design for Manufacturing

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    Iris Hui-Ru Jiang:
    Generic integer linear programming formulation for 3D IC partitioning. 321-324
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    Tariq E. L. Motassadeq, Vijay Sarathi, Syed Thameem, Mohamed Nijam:
    SPICE versus STA tools: Challenges and tips for better correlation. 325-328
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    Sheng Chou, Tsung-Yi Ho:
    OAL: An obstacle-aware legalization in standard cell placement with displacement minimization. 329-332
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    Frank Rogin, Rolf Drechsler, Steffen Rülke:
    Automatic debugging of System-on-a-Chip designs. 333-336
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    Shinyu Ninomiya, Masanori Hashimoto:
    Enhancement of grid-based spatially-correlated variability modeling for improving SSTA accuracy. 337-340

Session TB3 - Data Processing Architectures

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    Wei Wang, Weiqian Liang:
    A reconfigurable co-processor for GMM-based classifier. 343-346
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    Yongping Liu, Sakir Sezer, John V. McCanny:
    NFA decomposition and multiprocessing architecture for parallel regular expression processing. 347-350
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    Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns:
    DDR3 based lookup circuit for high-performance network processing. 351-354

Session FA1 - Low-Power Design Methodologies and IP Cores

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    Sohaib Majzoub, Resve A. Saleh, Steven J. E. Wilton, Rabab Kreidieh Ward:
    Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT. 357-360
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    Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler:
    Fast dynamic power estimation considering glitch filtering. 361-364
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    Ashok Narasimhan, Ramalingam Sridhar:
    Variation aware low power buffered interconnect design. 365-368
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    Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane:
    A low-power pairing-based cryptographic accelerator for embedded security applications. 369-372

Session FA2 - NoC Design Tools and Digital Signal Processing

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    Po-Tsang Huang, Wei Hwang:
    An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. 375-378
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    Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini:
    A floorplan-aware interactive tool flow for NoC design and synthesis. 379-382
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    Nuo Li, Nick van der Meijs:
    A Radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system. 383-386
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    Liang Lu, Máire O'Neill, Earl E. Swartzlander Jr.:
    ASIC evaluation of ECHO hash function. 387-390

Session FB1 - System Level Architecture Exploration

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    Moazzam Fareed Niazi, Khalid Latif, Hannu Tenhunen, Tiberiu Seceleanu:
    A DSL for the SegBus platform. 393-398
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    Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla:
    Accurate power estimation of hardware co-processors using system level simulation. 399-402
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    Maurizio Tranchero, Leonardo Maria Reyneri:
    Generating interacting synchronous and asynchronous designs from simulink descriptions. 403-406
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    Hari Kannan, Mihai Budiu, John D. Davis, Girish Venkataramani:
    Tuning SoCs using the global dynamic critical path. 407-411
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    Saeed Fouladi Fard, Amirhossein Alimohammad, Bruce F. Cockburn, Christian Schlegel:
    High path-count multirate Rayleigh fading channel simulator with time-multiplexed datapath. 412-415

Session FB2 - Imaging and Video Processing

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    Hoyoung Chang, Soojin Kim, Seonyoung Lee, Kyeongsoon Cho:
    High-performance architecture of H.264 integer-pixel motion estimation IP for real-time 1080HD video CODEC. 419-422
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    Michael Guarisco, Hassan Rabah, Yves Berviller, Serge Weber, Said Belkouch:
    FPGA-based SoC for transcoding H264/AVC-SVC with low latency and high bitrate entropy coding. 423-426
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    Norman Nolte, Sören Moch, Markus Kock, Peter Pirsch:
    Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams. 427-431
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    Yongseok Jin, Hyuk-Jae Lee:
    Pixel-Parallel SPIHT for frame memory compression. 432-435
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    Sang-Jin Lee, Kyung-Chang Park, Yeon-Ho Kim, Yun-ki Hong, Younggap You, Kyoung-Rok Cho, Tae Won Cho, Kamran Eshraghian:
    System-on-System (SoS) architecture for 3-D secure imaging. 436-439

Tutorials

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    Christian Haubelt:
    Designing multi-processor Systems-on-Chip. 443
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    Liam M. Devlin:
    Microwave IC design for broadband receivers. 444
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    Kaushik Roy:
    Design in the nano-scale Era: Low-power, reliability, and error resiliency. 445
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    Karsten Einwich, Christoph Grimm, Martin Barnasconi, Alain Vachoux:
    Introduction to the SystemC AMS DRAFT standard. 446

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