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11th VLSI Design 1998: Chennai, India

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  • Plenary Session
  • Physical Design
  • Digital Signal Processing
  • Test Synthesis
  • Analog / Physical Design
  • Banquet Session
  • VLSI Architecture and Arithmetic
  • Delay Test and Defect Analysis
  • Architecture and System Design Tools
  • Circuit Analysis and Design
  • Design Verification

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  11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India. IEEE Computer Society 1998, ISBN 0-8186-8224-8

Plenary Session

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  Robert W. Brodersen:
  Invited Address: The InfoPad Project: Review and Lessons Learned. 2-3
• 
  Teresa H. Meng:
  Invited Address: A Wireless Portable Video-On-Demand System. 4-

Low Power Design Methodologies

• 
  Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
  Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. 12-17
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  Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
  Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. 18-23
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  Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
  A Power Management Methodology for High-Level Synthesis. 24-19
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  Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar:
  Freedom: Statistical Behavioral Estimation of System Energy and Power. 30-36
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  Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
  Extensions to Programmable DSP architectures for Reduced Power Dissipation. 37-

Physical Design

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  Naveed A. Sherwani, Prashant Sawkar:
  Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout. 44-47
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  Zinaida V. Apanovich, Alexander G. Marchuk:
  Top-Down Approach to Technology Migration for Full-Custom Mask Layouts. 48-52
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  Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
  Technique for Planning of Terminal Locations of Leaf Cells in Cell-Based Design with Routing Considerations. 53-58
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  Subhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya:
  Partitioning VLSI Floorplans by Staircase Channels for Global Routing. 59-64
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  Sandip Das, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
  Routing of L-Shaped Channels, Switchboxes and Staircases in Manhattan-Diagonal Model. 65-

System Design and Synthesis

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  Neil Weste, David J. Skellern, Terry Percival:
  Invited Paper: Broadband U-NII Wireless Data. 72-77
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  Bengt Svantesson, Shashi Kumar, Ahmed Hemani:
  A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. 78-84
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  Anupam Basu, Raj S. Mitra, Peter Marwedel:
  Interface Synthesis for Embedded Applications in a Co Design Environment. 85-90
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  Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta:
  Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. 91-96
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  Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee:
  Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign. 97-

Digital Signal Processing

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  Amit Sinha, Mahesh Mehendale:
  mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. 104-109
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  Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh:
  Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. 110-115
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  Anteneh Alemu Abbo:
  An Embedded Processor for Integrated Navigation Receiver. 116-121
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  Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar:
  A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. 122-127
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  Srinivasan Balakrishnan, Soumitra Kumar Nandy:
  Arbitrary Precision Arithmetic - SIMD Style. 128-132
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  C. G. Hiremath, Sriram Jayasimha:
  Improving Concurrency for Cosine-modulated Filterbank Windowing. 133-

Analog Techniques

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  Srinivasan Venkatraman, Srikanth Natarajan, K. Radhakrishna Rao:
  A Low Power Video Frequency Continuous Time Filter. 140-144
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  C. Srinivasan:
  A Technique to Improve Capture Range of a PLL in PRML Read Channel. 145-149
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  Srinivasan Venkatraman, Srikanth Natarajan, K. Radhakrishna Rao:
  A New Tuning Scheme for Continuous Time Filters. 150-154
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  Gert Cauwenberghs:
  Design and VLSI Implementation of an Adaptive Delta-Sigma Modulator. 155-160
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  S. Pradeep Kiran, K. Radhakrishna Rao:
  A Novel Translinear Principle Based BiMOS Transconductor. 161-166
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  C. F. Prince, Vinita Vasudevan:
  Symbolic Analysis of Analog Integrated Circuits. 167-

Test Synthesis

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  Michael S. Hsiao, Gurjeet S. Saund, Elizabeth M. Rudnick, Janak H. Patel:
  Partial Scan Selection Based on Dynamic Reachability and Observability Information. 174-180
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  Arun Balakrishnan, Srimat T. Chakradhar:
  Peripheral Partitioning and Tree Decomposition for Partial Scan. 181-186
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  C. P. Ravikumar, Sumit Gupta, Akshay Jajoo:
  Synthesis of Testable RTL Designs. 187-192
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  Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey:
  Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits. 193-198
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  Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee:
  Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits. 199-204
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  Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya:
  Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. 205-

Logic Level CAD

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  Sumit Roy, Prithviraj Banerjee, Majid Sarrafzadeh:
  Partitioning sequential circuits for low power. 212-217
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  Pramit Chavda, James Jacob, Vishwani D. Agrawal:
  Optimizing Logic Design Using Boolean Transforms. 218-221
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  Aarti Gupta, Pranav Ashar:
  Integrating a Boolean Satisfiability Checker and BDDs for Combinational Equivalence Checking. 222-225
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  Abhijit Das, Samrat Sen, Mohan Rangan, Rupesh Nayak, G. N. Nandakumar:
  False Path Detection at Transistor Level. 226-229
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  Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan:
  Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. 230-233
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  Raghu Burra, Dinesh Bhatia:
  Timing Driven Multi-FPGA Board Partitioning. 234-

Analog / Physical Design

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  Adriano M. Pereira, Tales Cleber Pimenta, Robson L. Moreno, Edgar Charry R., Alberto M. Jorge:
  Design of a Measurement and Interface Integrated Circuit for Characterization of Switched Current Memory Cells. 240-243
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  Saeid Nooshabadi, G. S. Visweswaran, D. Nagchoudhuri:
  Current Mode Ternary D/A Converter. 244-248
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  Prakash Gopalakrishnan, Vinita Vasudevan:
  A Modified Line Expansion Algorithm for Device-level Routing of Analog Circuits. 249-252
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  Nagu R. Dhanwada, Ranga Vemuri:
  Constraint Allocation in Analog System Synthesis. 253-258
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  Gregory E. Beers, Lizy Kurian John:
  Novel Memory Bus Driver/Receiver Architecture for Higher Throughput. 259-264
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  Cyrus Bamji, Ravi Varadarajan:
  Incremental Autojogging using Range Spaces. 265-

Topics in Testing

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  V. Rajesh, Ajai Jain:
  Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms. 270-273
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  Sitaram Yadavalli, Sanjay Sengupta:
  Impact and Cost of Modeling Memories for ATPG for Partial Scan Designs. 274-278
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  Irith Pomeranz, Sudhakar M. Reddy:
  On Test Compaction Objectives for Combinational and Sequential Circuits. 279-284
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  Ananta K. Majhi, Vishwani D. Agrawal:
  Mixed-Signal Test. 285-288
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  Dilip Bhavsar:
  A Method for Synchronizing IEEE 1149.1 Test Access Port for Chip Level Testability Access. 289-292
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  Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
  Hybrid Testing Schemes Based on Mutual and Signature Testing. 293-

Banquet Session

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    Pallab K. Chatterjee:
    Keynote Address: The Networked Society - Enabled by DSP Solutions. 298-

Plenary Session

• 
  Jan M. Rabaey:
  Invited Address: Hybrid Reconfigurable Processors - The Road to Low-Power Consumption. 300-303
• 
  Charles G. Sodini, Jeffrey C. Gealow, Zubair A. Talib, Ichiro Masaki:
  Invited Address: Integrated Memory/Logic Architecture for Image Processing. 304-

VLSI Architecture and Arithmetic

• 
  S. Srivastava, S. C. Bose, B. P. Mathur, Arti Noor, Raj Singh, A. S. Mandal, K. Prabhakaran, Arindam Karmakar, Chandra Shekhar, Sudhir Kumar, Amit K. Agarwal:
  Evolution of Architectural Concepts and Design Methods of Microprocessors. 312-317
• 
  Giuseppe Ascia, Vincenzo Catania:
  A Framework for a Parallel Architecture Dedicated to Soft Computing. 318-321
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  Bernard Laurent, Gilles Bosco, Gabriele Saucier:
  Fast Arithmetic on Xilinx 5200 FPGA. 322-325
• 
  S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein:
  VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay. 326-329
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  R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili:
  A Low Power Floating Point Accumulator. 330-

Simulation and Synthesis

• 
  Rajeev Jain, Charles Chien, Etan G. Cohen, Leader Ho:
  Simulation and Synthesis of VLSI Communication Systems. 336-341
• 
  Partha S. Roop, Arcot Sowmya:
  CFSMcharts: A New Language for Microprocessor Based system Design. 342-346
• 
  Bharat P. Dave, Niraj K. Jha:
  COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. 347-354
• 
  Johnny Öberg, Axel Jantsch, Anshul Kumar:
  An Object-Oriented Concept for Intelligent Library Functions. 355-358
• 
  Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar:
  An Evolutionary Approach to System Redesign. 359-

Delay Test and Defect Analysis

• 
  Ananta K. Majhi, Vishwani D. Agrawal:
  Tutorial: Delay Fault Models and Coverage. 364-369
• 
  Amey Karkare, Manoj Singla, Ajai Jain:
  Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit. 370-373
• 
  S. Balajee, Ananta K. Majhi:
  Automated AC (Timing) Characterization for Digital Circuit Testing. 374-377
• 
  Vinay Dabholkar, Sreejit Chakravarty:
  Computing Stress Tests for Gate Oxide Shorts. 378-391
• 
  Wen-Ben Jone, Sunil R. Das:
  A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. 382-

Reconfigurable Processors and ASIC Design

• 
  Henry Selvaraj, Miroslawa Nowicka, Tadeusz Luba:
  Decomposition Strategies and their Performance in Fpga-Based Technology Mapping. 388-393
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  M. Bhaskar Sherigar, A. S. Mahadevan, K. Senthil Kumar, David S. Sumam:
  A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA. 394-399
• 
  Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar:
  Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. 400-405
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  P. S. Nagendra Rao, C. S. Jayathirtha, C. S. Raghavendra Prasad:
  New Net Models for Spectral Netlist Partitioning. 406
• 
  Atul Wokhlu, R. Venkat Krishna, Sandeep Agarwal:
  A Low Voltage Mixed Signal ASIC for Digital Clinical Thermometer. 412-

Architecture and System Design Tools

• 
  Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu:
  A VLSI ATM Switch Architecture for VBR Traffic. 420-427
• 
  Pradeep Prabhakaran, Prithviraj Banerjee:
  Simultaneous Scheduling, Binding and Floorplanning in High-level Synthesis. 428-434
• 
  Vinoo Srinivasan, Ranga Vemuri:
  A Retiming Based Relaxation Heuristic for Resource-Constrained Loop Pipelining. 435-441
• 
  Zhang Yang, Rajesh K. Gupta:
  A Case Analysis of System Partitioning and Its Relationship To High-Level Synthesis Tasks. 442-448
• 
  Debashis Saha, Anantha P. Chandrakasan:
  Web-based Distributed VLSI Design. 449-

Simulation and Test

• 
  Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
  MIX: A Test Generation System for Synchronous Sequential Circuits. 456-463
• 
  Seiji Kajihara, Kewal K. Saluja:
  On Test Pattern Compaction Using Random Pattern Fault Simulation. 464-469
• 
  Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal:
  Path Delay Testing: Variable-Clock Versus Rated-Clock. 470-475
• 
  Srikanth Venkataraman, W. Kent Fuchs, Janak H. Patel:
  Diagnostic Simulation of Sequential Circuits Using Fault Sampling. 476-481
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  C. S. Raghu, S. Sundaram:
  Distributed Logic Simulation Algorithm using Preemption of Inconsistent Events. 482-

Circuit Analysis and Design

• 
  Tony Tsang:
  A Compilable Read-Only-Memory Library for ASIC Deep Sub-micron Applications. 490-494
• 
  Rajesh S. Parthasarathy, Ramalingam Sridhar:
  Double Pass Transistor Logic for High Performance Wave Pipeline Circuits. 495-500
• 
  Pinaki Mazumder, Shriram Kulkarni, Mayukh Bhattacharya, Alejandro F. González:
  Circuit Design using Resonant Tunneling Diodes. 501-506
• 
  Rung-Bin Lin, Meng-Chiou Wu:
  A New Statistical Approach to Timing Analysis of VLSI Circuits. 507-

Logic and Circuit Synthesis

• 
  Vijay A. Nebhrajani, Nayan Suthar:
  Finite State Machines: A Deeper Look into Synthesis Optimization for VHDL. 516-521
• 
  Santanu Chattopadhyay, Parimal Pal Chaudhuri:
  Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis. 522-527
• 
  P. Srinivasa Rao, James Jacob:
  A Fast Two-level Logic Minimizer. 528-533
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  Cyrus Bamji, Manjit Borah:
  An Improved Cost Heuristic for Transistor Sizing. 534-

Design Verification

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  Gitanjali Swamy, Stephen A. Edwards, Robert K. Brayton:
  Efficient Verification and Synthesis using Design Commonalities. 542-551
• 
  Sreeranga P. Rajan, Masahiro Fujita:
  Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. 552-557
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  Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
  On-Chip Signature Checking for Embedded Memories. 558-563
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  Santanu Chattopadhyay, Parimal Pal Chaudhuri:
  Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence. 564-

Panel Session

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  Hugo De Man:
  Invited Address: Future Systems-on-a-Chip: Impact on Engineering Education. 572-577
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    Rajeev Jain:
    Panel: Challenges for Future Systems on a Chip. 578-

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