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13th VLSI Design 2000: Calcutta, India

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  • Tutorials
  • Thursday Plenary Talks
  • Session 1B: Formal Verification:
  • Session 2A: Digital Imaging I
  • Session 2C: Testing I
  • Session 3B: Layout & Floorplanning
  • Banquet Address
  • Session 4A: Digital Imaging II
  • Session 4C: Signal Integrity II
  • Session 5B: Verification
  • Session 6A: Analog / Mixed-signal Circuits
  • Session 6C: Testing IV

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  13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India. IEEE Computer Society 2000, ISBN 0-7695-0487-6

Tutorials

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  Mahesh Mehendale, Sunil D. Sherlekar:
  Power Reduction Techniques for Portable DSP Applications. 3
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  Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar:
  Theory and Applications of Cellular Automata for VLSI Design and Testing. 4
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  Rubin A. Parekhji:
  Test Techniques and Trade-offs for Embedded Cores and Systems. 5
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  Laurence Nagel, Jaijeet S. Roychowdhury:
  Computer-aided Design of RF Communication Systems: Techniques and Challenges. 6
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  Ramesh Harjani:
  Analog Circuits for Wireless Communications. 7
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  Melvin A. Breuer, Sandeep K. Gupta:
  New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. 8
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  Frank P. Higgins, Sudipta Bhawmik:
  Core Based ASIC Design. 10
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  Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake:
  Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. 11
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  Kaushik Roy, Khurram Muhammad:
  Low Power VLSI Signal Processing. 12

Keynote Address

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    Avtar Saini:
    Computing and Communication in the New Millennium. 15

Thursday Plenary Talks

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    Ajoy K. Bose:
    EDA-The Next Generation. 19
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    Raul Camposano, Warren Savage, John Chilton:
    IP Reuse in System on a Chip Design. 20-

Session 1A: Low Power Design

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  Liqiong Wei, Kaushik Roy, Vivek De:
  Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs. 24-29
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  M. N. Mahesh, Mahesh Mehendale:
  Low Power Realization of Residue Number System Based FIR Filters. 30-33
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  Savithri Sundareswaran, R. Venkatesan, S. Bhaskar:
  An Assertion Based Technique for Transistor Level Dynamic Power Estimation. 34-37
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  Russell E. Henning, Chaitali Chakrabarti:
  Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design. 38-43
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  Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang:
  A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. 44-49
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  Amit Sinha, Anantha P. Chandrakasan:
  Energy Aware Software. 50-

Session 1B: Formal Verification:

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  Pradip Bose, Jacob A. Abraham:
  Performance and Functional Verification of Microprocessors. 58-63
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  Partha S. Roop, Arcot Sowmya, S. Ramesh:
  Automatic Component Matching Using Forced Simulation. 64-69
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  Dipankar Sarkar:
  Status Condition Analysis during Data Path Verification of Sequential Circuits. 70-75
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  Basant Rajan, R. K. Shyamasundar:
  Modeling VHDL in Multiclock ESTEREL. 76-83
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  Abhijit Ghosh, Ranga Vemuri:
  Formal Verification of Synthesized Mixed Signal Designs Using *BMDs. 84-

Session 1C: Embedded Systems I

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  Arvind Rajawat, M. Balakrishnan, Anshul Kumar:
  nterface Synthesis: Issues and Approaches. 92
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  T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik:
  Processor Evaluation in an Embedded Systems Design Environment. 98-103
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  Rainer Schaffer, Renate Merker, Francky Catthoor:
  Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. 104-109
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  Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan:
  Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. 110-113
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  Robert P. Dick, Niraj K. Jha:
  COWLS: Hardware-Software Co-Synthesis of Distributed Wireless Low-Power Embedded Client-Server Systems. 114-

Session 2A: Digital Imaging I

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  Werner Metz, Tinku Acharya:
  Challenges of Merging Digital Imaging and Wireless Communication. 122-127
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  Arun K. Majumdar, Nirav Patel:
  Design of an ASIC for Straight Line Detection in an Image. 128-133
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  Sandip Sarkar:
  Digital Imaging with Wireless Data Services. 134-139
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  Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury:
  GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images. 140-143
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  Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury:
  Scalable Pipelined Micro-Architecture for Wavelet Transform. 144-

Session 2B: Signal Integrity I

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  Akis Doganis:
  Interconnect Statistical Modeling: Structures and Measurement Methodologies. 150
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  Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw:
  Design and Analysis of Power Distribution Networks with Accurate RLC Models. 151-155
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  Jinseong Choi, Sungjun Chun, Nanju Na, Madhavan Swaminathan, Larry D. Smith:
  A Methodology for the Placement and Optimization of Decoupling Capacitors for Gigahertz Systems. 156-161
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  Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Vivek Tiwari:
  Inductive Noise Reduction at the Architectural Level. 162-167
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  Shiyou Zhao, Kaushik Roy:
  Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits. 168-

Session 2C: Testing I

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  Manuel A. d'Abreu:
  Manufacturing and Test Considerations in System-On-Chip Designs. 176-177
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  Jitendra Khare, Hans T. Heineken, Manuel d'Abreu:
  Cost Trade-Offs in System On Chip Designs. 178-184
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  Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken:
  Manufacturability and Testability Oriented Synthesis. 185-191
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  Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, Manuel d'Abreu:
  Maximizing Wafer Productivity Through Layout Optimization. 192-197
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  Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab:
  Hierarchical Test Generation for Systems On a Chip. 198-

Session 3A: High-level Synthesis

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  Chittaranjan A. Mandal, R. M. Zimmer:
  A Genetic Algorithm for the Synthesis of Structured Data Paths. 206-211
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  Sriram Govindarajan, Vinoo Srinivasan, Preetham Lakshmikanthan, Ranga Vemuri:
  A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures. 212-219
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  Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana:
  High-Level Synthesis with Variable-Latency Components. 220-227
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  Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan:
  CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. 228-233
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  Abdel Ejnioui, N. Ranganathan:
  Design Partitioning on Single-Chip Emulation Systems. 234-239
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  Rajeev Murgai:
  Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. 240-

Session 3B: Layout & Floorplanning

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  Abdel Ejnioui, N. Ranganathan:
  Routing on Switch Matrix Multi-FPGA Systems. 248-253
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  Ranjit K. Dash, T. Pramod, Vinita Vasudevan, M. Ramakrishna:
  A Transistor Level Placement Tool for Custom Cell Generation. 254-257
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  Abhijit Das:
  On the Transistor Sizing Problem. 258-261
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  Sushil Chandra Jain, Shashi Kumar, Anshul Kumar:
  Evaluation of Various Routing Architectures for Multi-FPGA Boards. 262-267
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  Yu-Liang Wu, Wangning Long, Hongbing Fan:
  A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. 268-273
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  Swarup Bhunia, Subhashis Majumder, Ayan Sircar, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
  Topological Routing Amidst Polygonal Obstacles. 274-279
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  Helvio P. Peixoto, Margarida F. Jacome, Ander Royo:
  A Tight Area Upper Bound for Slicing Floorplans. 280-

Session 3C: Testing II

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  Hideo Fujiwara:
  A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. 288-293
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  Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
  Test Transformation to Improve Compaction by Statistical Encoding. 294-299
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  Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara:
  Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. 300-305
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  Vishwani D. Agrawal:
  Choice of Tests for Logic Verification and Equivalence Checking. 306-311
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  Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham:
  Automatic Validation Test Generation Using Extracted Control Models. 312-

Banquet Address

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    John Scarisbric:
    DSP-The Real Time Technology for the New Millennium. 321-

Friday Plenary Talk

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    Grant Martin:
    Surviving the SOC Revolution: The Platform Approach to SOC Design. 325-

Session 4A: Digital Imaging II

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  Sabyasachi Dey, Bhargab B. Bhattacharya, Malay Kumar Kundu, Tinku Acharya:
  A Fast Algorithm for Computing the Euler Number of an Image and its VLSI Implementation. 330-335
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  Rajesh T. N. Rajaram, Vinita Vasudevan:
  Optimization of the One-Dimensional Full Search Algorithm and Implementation Using an EPLD. 336-341
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  Bedabrata Pain, Guang Yang, Monico Ortiz, Kenneth McCarty, Julie Heynssens, Bruce Hancock, Thomas Cunningham, Chris Wrigley, Charlie Ho:
  A Single-Chip Programmable Digital CMOS Imager with Enhanced Low-Light Detection Capability. 342-349

Session 4B: Design

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  Santanu Dutta, Deepak Singh, Essam Abu-Ghoush, Vijay Mehra:
  Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications. 350-359
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  Fu-Chiung Cheng, Chuin-Ren Wang:
  Specification and Design of a Quasi-Delay-Insensitive Java Card. 356-361
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  Santanu Das:
  Trends in Communication Technology and its Impact on Semiconductor. 362-

Session 4C: Signal Integrity II

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  Sachin S. Sapatnekar:
  Capturing the Effect of Crosstalk on Delay. 364-369
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  N. S. Nagaraj, Frank Cano, Duane Young, Deepak Vohra, Manoj Das:
  A Practical Approach to Crosstalk Noise Verification of Static CMOS Designs. 370-375
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  Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal:
  Inductance Characterization of Small Interconnects Using Test-Signal Method. 376-

Session 5A: Testing III

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  Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel:
  Zero-Aliasing Space Compression using a Single Periodic Output and its Application to Testing of Embedded Cores. 382-391
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  Irith Pomeranz, Sudhakar M. Reddy:
  On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. 392-397
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  Surendra Bommu, Srimat T. Chakradhar, Kiran B. Doreswamy:
  Resource-Constrained Compaction of Sequential Circuit Test Sets. 398-405
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  Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap:
  Testing Flash Memories. 406-411
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  Frank Mayer, Albrecht P. Stroele:
  A Versatile BIST Technique Combining Test Registers and Accumulators. 412-

Session 5B: Verification

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  Subir K. Roy, Hiroaki Iwashita, Tsuneo Nakata:
  Dataflow Analysis for Resource Contention and Register Leakage Properties. 418-423
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  Subhash Chandra, Rajat Moona:
  Retargetable Functional Simulator Using High Level Processor Models. 424-429
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  Peter M. Maurer, William J. Schilp:
  State-Machine Based Logic Simulation Using Three Logic Values. 430-435
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  Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
  Hierarchical Error Diagnosis Targeting RTL Circuits. 436-441
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  Aarti Gupta, Pranav Ashar:
  Fast Error Diagnosis for Combinational Verification. 442-448
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  Yang Xia, Pranav Ashar:
  Verification of a Combinational Loop Based Arbitration Scheme in a System-On-Chip Integration Architecture. 449-

Session 5C: Embedded Systems II

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  Anil Sharma, C. P. Ravikumar:
  Efficient Implementation of ADPCM Codec. 456-461
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  C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma:
  Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. 462-467
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  Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar:
  A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. 468-

Session 6A: Analog / Mixed-signal Circuits

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  Ruchir Puri, Ching-Te Chuang:
  SOI Digital Circuits: Design Issues. 474-479
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  Sanjeev Kumar Maheshwari, R. S. Krishanan, G. S. Visweswaran:
  Jitter Estimation Methodology for Clock Chips. 480-482
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  Sanjeev Kumar Maheshwari, G. S. Visweswaran:
  A 3.3V Compatible 2.5V TTL-to-CMOS Bidirectional I/O Buffer. 484-487
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  B. Senapati, Chinmay K. Maiti, Nirmal B. Chakrabarti:
  Silicon Heterostructure Devices for RF Wireless Communication. 488-491
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  Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi:
  Design of OTA Based Field Programmable Analog Array. 492-497
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  Mayukh Bhattacharya, Pinaki Mazumder:
  Convergence Issues in Resonant Tunneling Diode Circuit Simulation. 499-

Session 6B: Synthesis and Timing Analysis

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  Bogdan J. Falkowski, Sudha Kannurao:
  Spectral Theory of Disjunctive Decomposition for Balanced Boolean Functions. 506-511
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  B. Suresh, Biswadeep Chaterjee, R. Harinath:
  Synthesizable RAM-Alternative to Low Configuration Compiler Memory for Die Area Reduction. 512-517
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  Eugene Goldberg, Alexander Saldanha:
  Timing Analysis with Implicitly Specified False Paths. 518-522
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  Kamal S. Khouri, Niraj K. Jha:
  Clock Selection for Performance Optimization of Control-Flow Intensive Behaviors. 523-529
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  Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
  Performance Analysis of Systems with Multi-Channel Communication Architectures. 530-537
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  Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta:
  An ASIC for Cellular Automata Based Message Authentication. 538-

Session 6C: Testing IV

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  Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta:
  Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits. 544-549
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  Sasikumar Cherubal, Abhijit Chatterjee:
  An Efficient Hierarchical Fault Isolation Technique for Mixed-Signal Boards. 550-555
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  Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee:
  Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. 556-561
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  Kolin Paul, Dipanwita Roy Chowdhury:
  Application of GF(2p) CA in Burst Error Correcting Codes. 562-567
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  Gloria Huertas, Diego Vázquez, Adoración Rueda, José L. Huertas:
  Built-In Self-Test in Mixed-Signal ICs: A DTMF Macrocell. 568-571
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  Jeongjin Roh, Jacob A. Abraham:
  A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters. 572-

VLSI Design 1999 Paper (late arrival)

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  Juha Plosila, Tiberiu Seceleanu:
  Design of Synchronous Action Systems. 578-583

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