Journal of Electronic Testing, Volume 41 (original) (raw)

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Volume 41, Number 1, February 2025

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    Vishwani D. Agrawal:
    Editorial. 1
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    2024 Reviewers. 3-4
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    Arjun Lal Kumawat, Anukul Pandey, N. S. Raghava:
    Design of a Low Noise Amplifier Based on Novel Monolayer Graphene FET. 5-14
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    Vipin Kumar Sharma, Abhishek Kumar:
    Read & Write Stability of CNTFET 6T SRAM Cell: A Comprehensive Analysis. 15-25
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    Jie Fu, Kai Sun, Hanbo Jia, Da Fu, Jingyuan Xu, Xuan Guo:
    Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment. 27-39
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    Shounak Rushikesh Sugave, Yogesh R. Kulkarni, Balaso Jagdale, Vitthal Gutte:
    Fault-Aware Test Case Prioritization in Software Testing Using Jaya Archimedes Optimization Algorithm. 41-61
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    Hamed A. Mahmood, Shawkat Sabah Khairullah:
    Design and Simulation of a Dependable Architecture Using Triple Modular Redundancy for Embedded Cyber-Physical Systems. 63-74
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    Yuchao Liu, Liang Yao, Wenjing Zhang, Yuhao Wang, Xinkai Jiang, Fusen Li, Qiu Xu:
    SEU Fault Injection Strategy for SRAM-based FPGA User Memory Based on Dual-Circuit Model. 75-84
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    M. Shafkat M. Khan, Chengjie Xi, Nitin Varshney, Je-Hyeong Bahk, Navid Asadizanjani:
    Inherent Hardware Identifiers: Advancing IC Traceability and Provenance in the Multi-Die Era. 85-107

Volume 41, Number 2, April 2025

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    Vishwani D. Agrawal:
    Editorial. 109-110
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    Chloe Tain, Savita Patil, Hussain Al-Asaad:
    Survey of Verification of RISC-V Processors. 111-138
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    K. N. Baluprithviraj, Vijayachitra Senniappan, N. Mahesh:
    Logic Locking Based Configurable Obfuscation Cell for Enhanced IC Security. 139-146
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    Xiaozhi Du, Kai Chen, Zongbin Qiao:
    A Multi-Objective Test Scenario Prioritization Method Based on UML Activity Diagram. 147-171
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    Gajender Rao, Deepak Nandal:
    Test Case Optimization using Machine Learning based Hybrid Meta-Heuristic Approach. 173-192
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    Enrico Magliano, Alessandro Savino, Stefano Di Carlo:
    Real-time Embedded System Fault Injector Framework for Micro-architectural State Based Reliability Assessment. 193-208
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    Hanieh Jafarzadeh, Florian Klemme, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
    Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage. 209-219
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    Suman Biswas, Gautam Kumar Mahanti, Nilanjan Chattaraj:
    Extreme Learning Machine Model For Multi-Fault Diagnosis of Analog Circuits. 221-239
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    Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak:
    Hybrid Ring Generators for In-System Testing. 241-253

Volume 41, Number 3, June 2025

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    Vishwani D. Agrawal:
    Editorial. 255-256
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    Sami El Amraoui, Aghiles Douadi, Régis Leveugle, Paolo Maistri:
    On the Harmonic Locking of Ring Oscillators under Single ElectroMagnetic Pulsed Fault Injection in FPGAs. 257-272
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    Junchao Chen, Li Lu, Marko S. Andjelkovic, Fabian Luis Vargas, Milos Krstic:
    Dynamic Fault Mitigation for Space Radiation Using Fault Injection and Machine Learning. 273-285
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    Marko S. Andjelkovic, Milos Krstic:
    Analysis and Modeling of Single Event Transient Generation in Standard Combinational Cells. 287-302
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    Munish Malik, Neelam Rup Prakash, Ajay Kumar, Jasbir Kaur, Amit Singh, Kavita Monga:
    Analyzing the Effectiveness of Various NMOS Layouts for Total Ionizing Dose Hardening in 180nm CMOS. 303-312
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    G. Prabu, C. Sujatha, J. Erin Shine, T. Arulkumar:
    SFFHO: Development of Statistical Fitness-based Fire Hawk Optimizer for Software Testing and Maintenance Approach using Adaptive Deep Learning Method. 313-338
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    Zhenqiu Li, Tingting Wu, Sihui Chen, Mingyue Jiang, Zuohua Ding, Yunwei Dong:
    Cross-Domain Multi-Label Prediction of Metamorphic Relation Patterns Leveraging Multimodal Features. 339-358
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    Rezgar Sadeghi, Amirhossein Ilkhani, Amirhosein Yazdanpanah:
    Uncertainty-Aware Crosstalk Predictors for Adaptive Reliability in Core Interconnects. 359-371
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    Riaz-ul-haque Mian, Foisal Ahmed, Yoshito Hagihara, Souma Yamane:
    Custom-Adaptive Kernel Strategies for Gaussian Process Regression in Wafer-Level Modeling and FPGA Delay Analysis. 373-386
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    Amit Mondal, Tuhina Samanta:
    Artificial Neural Network Based Prediction Model for IR Drop Measurement in a VLSI Power Delivery Network. 387-406

Volume 41, Number 4, August 2025

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    Vishwani D. Agrawal:
    Editorial. 407-408
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    Sushil Doranga Joins JETTA Editorial Board. 409
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    Xianjun Du, Shenglong Jia, Yuxiang Hu, Yaqi Wang:
    Fault Diagnosis of Analog Circuits Using an Improved BiTCN Combined with BiLSTM. 411-430
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    Yao Li, Yan Gao, GuoZhen Hu, Guoqing Huang, Liang Zhao, Yan Sun, Weihua Yu:
    Failure Analysis and Power-on Sequence Optimization for InP DHBT Stacked Amplifiers. 431-439
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    Zhijun Yue, Ling He, Jin He, Guanci Yang, Yi Yang, Yinhong An:
    A Method of Redundant Feature Suppression in Circuit Output Positions for Analog Circuit Soft and Hard Fault Diagnosis. 441-465
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    Vijaypal Singh Rathor, Akshat Rastogi:
    HT-Pred: An Extensive Methodology for Dataset Preparation and Hardware Trojan Prediction using Gate-Level Netlist. 467-482
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    Wenbing Xie, Ruixue Guan, Fanyue Yu, Yiming Zhang:
    PrecIRisc: A High-Precision and Low-Bloat Dynamic Binary Instrumentation Tailored for RISC Architectures. 483-502
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    Aditya Kumar Singh Pundir, Pallavi Singh, Ramesh Kumar, Manish Kumar Singla:
    Modelling, Simulation, and FPGA Implementation of an Augmented Memory Built-in Self-Test Based Design for Bit-Oriented Memory. 503-523
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    Djiddo Ali Oumar, Mahamat Issa Boukhari, Stéphane Capraro, D. Piétroy, J. P. Chatelon, Jean Jacques Rousseau:
    Calibration Impact on the Characterization of Components at Temperature. 525-543
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    Sana Nasri, Nadeem Ahmad, Qurat Ul Ain Aini, Atif Qayyum, Naeem Ul Islam:
    A YOLOv9: Deep Learning-based Framework Defect Detection Method for PCBs. 545-559
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    Xudong Song, Xiumin Song:
    SNF-YOLOv8: A Lightweight PCB Defect Detection Algorithm base on Multiscale Feature Fusion and Attention Scale Sequence Fusion. 561-573
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    Zong-Si Wu, Jenq-Shiou Leu:
    Firmware-Driven Adaptive Clock Tuning for Electromagnetic Interference Tolerance in Automotive Systems. 575-579

Volume 41, Number 5, December 2025

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    Vishwani D. Agrawal:
    Editorial. 581-582
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    2024 JETTA-TTTC Best Paper Award. 583-585
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    Na Yang, Shuhao Jiang, Yun Wang, Qing Miao:
    SD2CI: A Structure-driven Approach for Detecting Silent Data Corruption Instructions. 587-602
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    Jun Yuan, Liangrui Zhang, Yuyang Zhang:
    Chebyshev-based Algorithm: Achieving Fast ADC Static Parameter Testing Using a Low-precision Signal Source. 603-613
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    María Isabel Dieste-Velasco:
    Enhanced Monte Carlo-Based Uncertainty Quantification in Electronic Circuits. 615-629
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    Sanjiv Sharma, Ankur Bhardwaj, Amar Singh, Vinay Singh:
    Enhanced Moth Flame Optimization Algorithm Entropy-Based Centroid SVM-Based Software Defect Prediction. 631-649
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    Bahman Arasteh, Faruk Bulut, Ibrahim Furkan Ince, Seyed Salar Sefati, Huseyin Kusetogullari, Farzad Kiani:
    A Metaheuristic and Neural Network-Based Framework for Automated Software Test Oracles Under Limited Test Data Conditions. 651-671
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    Bahman Arasteh, Seyed Salar Sefati, Peri Gunes, Vahid Hosseinzadeh, Farzad Kiani:
    A Program-Output Estimator for Software Testing Using Program Analysis and Deep Learning Algorithms. 673-689
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    Kiran Kumar Bhadavath, Vijayakumar Sajjan, Narsaiah Domala, Ashok Kumar Konduru, Sreedhar Jadapalli, Ramadevi Vemula:
    Enhancing Digital VLSI Circuit Debugging with Unified Neighbor aware Graph Neural Network Based Automated Error Detection. 691-708
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    Shreevatsa Alawandi, Kaushik Mallibhat, Umer Kudachi, Aishwarya Beedanal:
    PCB Defects: A Unified Survey of Trends, Detection Techniques, and Limitations through Systematic Literature Review. 709-787
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    Shreevatsa Alawandi, Kaushik Mallibhat, Umer Kudachi, Aishwarya Beedanal:
    Correction: PCB Defects: a Unified Survey of Trends, Detection Techniques, and Limitations Through Systematic Literature Review. 789
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    Gustavo Aguirre, Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli:
    A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers. 791-803
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    Gustavo Paz Platcheck, Guilherme Schwanke Cardoso, Tiago R. Balen:
    Variability and Analog Parameter Characterization in Enclosed Layout Transistors. 805-821

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