dblp: Integration, Volume 44 (original) (raw)

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Volume 44, Number 1, January 2011

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    Lihong Zhang, Zheng Liu:
    Directly performance-constrained template-based layout retargeting and optimization for analog integrated circuits. 1-11
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    Mehrdad Khatir, Alireza Ejlali, Amir Moradi:
    Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles. 12-21
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    Syed Rafay Hasan, Normand Bélanger, Yvon Savaria, M. Omair Ahmad:
    All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. 22-38
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    Cristian Ferent, Alex Doboli:
    Measuring the uniqueness and variety of analog circuit design features. 39-50
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    Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler:
    Debugging reversible circuits. 51-61
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    Massimo Alioto, Gaetano Palumbo, Massimo Poli:
    Optimized design of parallel carry-select adders. 62-74
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    Chih-Peng Fan, Chia-Hao Fang:
    Efficient RC low-power bus encoding methods for crosstalk reduction. 75-86
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    Chung-Chieh Kuo, Chia-Chun Tsai, Trong-Yen Lee:
    Pattern-matching-based X-architecture zero-skew clock tree construction with X-Flip technique and via delay consideration. 87-101

Volume 44, Number 2, March 2011

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    Bo Ye, Qian Zhao, Duo Zhou, Xiaohua Wang, Min Luo:
    Test data compression using alternating variable run-length code. 103-110
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    Amin Farshidi, Laleh Behjat, Logan M. Rakai, Bahareh Fathi:
    A pre-placement individual net length estimation model and an application for modern circuits. 111-122
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    Ali Jahanian, Morteza Saheb Zamani, Hamid Safizadeh:
    Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology. 123-135
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    San-Fu Wang, Yuh-Shyan Hwang, Shou-Chung Yan, Jiann-Jong Chen:
    A new CMOS wideband low noise amplifier with gain control. 136-143
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    Özsun S. Sönmez, Günhan Dündar:
    Simulation-based analog and RF circuit synthesis using a modified evolutionary strategies algorithm. 144-154

Volume 44, Number 3, June 2011

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    Keivan Navi, Horialsadat Hossein Sajedi, Reza Faghih Mirzaee, Mohammad Hossein Moaiyeri, Ali Jalali, Omid Kavehei:
    High-speed full adder based on minority function and bridge style for nanoscale. 155-162
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    Dimitris Bakalis, Haridimos T. Vergos, Anastasia Spyrou:
    Efficient modulo 2n±1 squarers. 163-174
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    Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay:
    Low power finite state machine synthesis using power-gating. 175-184
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    Song Jin, Yinhe Han, Huawei Li, Xiaowei Li:
    Statistical lifetime reliability optimization considering joint effect of process variation and aging. 185-191
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    M. Xu, Gary Gréwal, Shawki Areibi:
    StarPlace: A new analytic method for FPGA placement. 192-204
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    Jia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu:
    Capture-power-aware test data compression using selective encoding. 205-216
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    Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael:
    Improved diagnosis using enhanced fault dominance. 217-228
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    Armin Jalili, Sayed Masoud Sayedi, J. Jacob Wikner, Abolghasem Zeidaabadi Nezhad:
    A nonlinearity error calibration technique for pipelined ADCs. 229-241
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    Shu-Yi Wong, Chunhong Chen:
    Power efficient multi-stage CMOS rectifier design for UHF RFID tags. 242-255

Volume 44, Number 4, September 2011

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    Kris Gaj, Rainer Steinwandt:
    Hardware architectures for algebra, cryptology, and number theory. 257-258
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    Kazuo Sakiyama, Miroslav Knezevic, Junfeng Fan, Bart Preneel, Ingrid Verbauwhede:
    Tripartite modular multiplication. 259-269
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    Kimmo Järvinen:
    Optimized FPGA-based elliptic curve cryptography processor for high-speed applications. 270-279
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    Junfeng Fan, Lejla Batina, Ingrid Verbauwhede:
    Design and design methods for unified multiplier and inverter and its application for HECC. 280-289
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    Andy Rupp, Thomas Eisenbarth, Andrey Bogdanov, Oliver Grieb:
    Hardware SLE solvers: Efficient building blocks for cryptographic and cryptanalyticapplications. 290-304
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    Yang Sun, Joseph R. Cavallaro:
    Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder. 305-315

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