IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 34 (original) (raw)

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Volume 34, Number 1, January 2015

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    Vijaykrishnan Narayanan, Charles J. Alpert, Sara Dailey:
    Editorial. 1
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    Sachhidh Kannan, Naghmeh Karimi, Ozgur Sinanoglu, Ramesh Karri:
    Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures. 2-15
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    Sanghyuk Jung, Yong Ho Song:
    Garbage Collection for Low Performance Variation in NAND Flash Storage Systems. 16-28
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    Yan Luo, Bhargab B. Bhattacharya, Tsung-Yi Ho, Krishnendu Chakrabarty:
    Design and Optimization of a Cyberphysical Digital-Microfluidic Biochip for the Polymerase Chain Reaction. 29-42
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    Rene Broich, Hans Grobler:
    Soft-Core Dataflow Processor Architecture Optimized for Radar Signal Processing. 43-51
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    Roberto Sierra, Carlos Carreras, Gabriel Caffarena, Carlos A. López Bario:
    A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. 52-62
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    Zheng Zhang, Xiu Yang, Ivan V. Oseledets, George E. Karniadakis, Luca Daniel:
    Enabling High-Dimensional Hierarchical Uncertainty Quantification by ANOVA and Tensor-Train Decomposition. 63-76
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    Paolo Maffezzoni, Bichoy Bahr, Zheng Zhang, Luca Daniel:
    Analysis and Design of Weakly Coupled LC Oscillator Arrays Based on Phase-Domain Macromodels. 77-85
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    Yaoyao Lin, Emad Gad:
    Formulation of the Obreshkov-Based Transient Circuit Simulator in the Presence of Nonlinear Memory Elements. 86-94
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    Hong-Yan Su, Chieh-Chu Chen, Yih-Lang Li, An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang:
    A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding. 95-108
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    Xiaoxiao Wang, LeRoy Winemberg, Donglin Su, Dat Tran, Saji George, Nisar Ahmed, Steve Palosh, Allan Dobin, Mark Tehranipoor:
    Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor. 109-121
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    Mukesh Agrawal, Krishnendu Chakrabarty, Randy Widialaksono:
    Reuse-Based Optimization for Prebond and Post-Bond Testing of 3-D-Stacked ICs. 122-135
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    Ran Wang, Krishnendu Chakrabarty, Sudipta Bhawmik:
    Interconnect Testing and Test-Path Scheduling for Interposer-Based 2.5-D ICs. 136-149
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    Qian Wang, Xiaoyu Song, William N. N. Hung, Ming Gu, Jiaguang Sun:
    Scalable Verification of a Generic End-Around-Carry Adder for Floating-Point Units by Coq. 150-154
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    Sotirios Xydis, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano:
    SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level Synthesis. 155-159

Volume 34, Number 2, February 2015

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    Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang, Hui-Fang Tsao:
    Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits. 161-172
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    Lengfei Han, Xueqian Zhao, Zhuo Feng:
    An Adaptive Graph Sparsification Approach to Scalable Harmonic Balance Analysis of Strongly Nonlinear Post-Layout RF Circuits. 173-185
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    Soumyasanta Laha, Savas Kaya, David W. Matolak, William Rayess, Dominic DiTomaso, Avinash Karanth Kodi:
    A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects. 186-198
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    Po-Hsun Wu, Mark Po-Hung Lin, Tung-Chieh Chen, Ching-Feng Yeh, Xin Li, Tsung-Yi Ho:
    A Novel Analog Physical Synthesis Methodology Integrating Existent Design Expertise. 199-212
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    Markus Meissner, Lars Hedrich:
    FEATS: Framework for Explorative Analog Topology Synthesis. 213-226
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    Mengying Zhao, Lei Jiang, Liang Shi, Youtao Zhang, Chun Jason Xue:
    Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation. 227-237
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    Cláudio Machado Diniz, Muhammad Shafique, Sergio Bampi, Jörg Henkel:
    A Reconfigurable Hardware Architecture for Fractional Pixel Interpolation in High Efficiency Video Coding. 238-251
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    Donghwa Shin, Massimo Poncino, Enrico Macii, Naehyuck Chang:
    A Statistical Model-Based Cell-to-Cell Variability Management of Li-ion Battery Pack. 252-265
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    Heechun Park, Taewhan Kim:
    Synthesis of TSV Fault-Tolerant 3-D Clock Trees. 266-279
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    Mark Po-Hung Lin, Chih-Cheng Hsu, Yu-Chuan Chen:
    Clock-Tree Aware Multibit Flip-Flop Generation During Placement for Power Optimization. 280-292
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    Giovanni Mariani, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano:
    DeSpErate++: An Enhanced Design Space Exploration Framework Using Predictive Simulation Scheduling. 293-306
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    Minghua Tang, Xiaola Lin, Maurizio Palesi:
    An Offline Method for Designing Adaptive Routing Based on Pressure Model. 307-320

Volume 34, Number 3, March 2015

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    Dani Tannir:
    Direct Sensitivity Analysis of Nonlinear Distortion in RF Circuits Using Multidimensional Moments. 321-331
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    Reza Azarderakhsh, Mehran Mozaffari Kermani, Kimmo Järvinen:
    Secure and Efficient Architectures for Single Exponentiations in Finite Fields Suitable for High-Performance Cryptographic Applications. 332-340
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    Sandeep Koranne:
    Design and Analysis of Silicon Photonics Wave Guides Using Symbolic Methods. 341-353
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    Qing Duan, Jun Zeng, Krishnendu Chakrabarty, Gary Dispoto:
    Accurate Predictions of Process-Execution Time and Process Status Based on Support-Vector Regression for Enterprise Information Systems. 354-366
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    Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
    Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy. 367-380
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    Muhammet Mustafa Ozdal, Aamer Jaleel, Paolo Narváez, Steven M. Burns, Ganapati Srinivasa:
    Wavelet-Based Trace Alignment Algorithms for Heterogeneous Architectures. 381-394
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    Gabriela Ciuprina, Daniel Ioan, Rick Janssen, Edwin van der Heijden:
    MEEC Models for RFIC Design Based on Coupled Electric and Magnetic Circuits. 395-408
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    Hengliang Zhu, Yuanzhe Wang, Frank Liu, Xin Li, Xuan Zeng, Peter Feldmann:
    Efficient Transient Analysis of Power Delivery Network With Clock/Power Gating by Sparse Approximation. 409-421
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    Naval Gupte, Jia Wang:
    Secure Power Grid Simulation on Cloud. 422-432
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    Bei Yu, Kun Yuan, Duo Ding, David Z. Pan:
    Layout Decomposition for Triple Patterning Lithography. 433-446
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    Tao Lin, Chris C. N. Chu, Joseph R. Shinnerl, Ismail Bustany, Ivailo Nedelchev:
    POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints. 447-459
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    Yen-Ting Yu, Geng-He Lin, Iris Hui-Ru Jiang, Charles C. Chiang:
    Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction. 460-470
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    Iou-Jen Liu, Shao-Yun Fang, Yao-Wen Chang:
    Stitch-Aware Routing for Multiple E-Beam Lithography. 471-482
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    Emanuele Giaquinta, Anadi Mishra, Laura Pozzi:
    Maximum Convex Subgraphs Under I/O Constraint for Automatic Identification of Custom Instructions. 483-494
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    Ibrahim N. Hajj:
    On Device Modeling for Circuit Simulation With Application to Carbon-Nanotube and Graphene Nano-Ribbon Field-Effect Transistors. 495-499

Volume 34, Number 4, April 2015

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    Azadeh Davoodi, Jiang Hu, Muhammet Mustafa Ozdal, Cliff C. N. Sze:
    Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. 501
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    Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
    Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. 502-514
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    Rickard Ewetz, Cheng-Kok Koh:
    Cost-Effective Robustness in Clock Networks Using Near-Tree Structures. 515-528
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    Shang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho:
    Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips. 529-539
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    Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
    Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs. 540-553
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    Caleb Serafy, Ankur Srivastava:
    TSV Replacement and Shield Insertion for TSV-TSV Coupling Reduction in 3-D Global Placement. 554-562
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    Markus Ahrens, Michael Gester, Niko Klewinghaus, Dirk Müller, Sven Peyer, Christian Schulte, Gustavo E. Téllez:
    Detailed Routing Algorithms for Advanced Technology Nodes. 563-576
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    Yu-Guang Chen, Wan-Yu Wen, Yiyu Shi, Wing-Kai Hon, Shih-Chieh Chang:
    Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints. 577-588
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    Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
    Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. 589-602
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    Emad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia:
    Model-Driven Design of Network Aspects of Distributed Embedded Systems. 603-614
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    Ching-Yi Huang, Zheng-Shan Yu, Yung-Chun Hu, Tung-Chen Tsou, Chun-Yao Wang, Yung-Chih Chen:
    Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits. 615-628
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    Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
    An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips. 629-641
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    Wenxing Zhu, Jianli Chen, Zheng Peng, Genghua Fan:
    Nonsmooth Optimization Method for VLSI Global Placement. 642-655
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    Mehran Mozaffari Kermani, Niranjan Manoharan, Reza Azarderakhsh:
    Reliable Radix-4 Complex Division for Fault-Sensitive Applications. 656-667
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    Fotis Vartziotis, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Arvind Jain, Rubin A. Parekhji:
    Time-Division Multiplexing for Testing DVFS-Based SoCs. 668-681

Volume 34, Number 5, May 2015

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    Jingwei Lu, Hao Zhuang, Pengwen Chen, Hongliang Chang, Chin-Chih Chang, Yiu-Chung Wong, Lu Sha, Dennis J.-H. Huang, Yufeng Luo, Chin-Chi Teng, Chung-Kuan Cheng:
    ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits. 685-698
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    Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
    Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization. 699-712
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    Hui Geng, Jianming Liu, Pei-Wen Luo, Liang-Chia Cheng, Steven L. Grant, Yiyu Shi:
    Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach. 713-725
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    Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan:
    Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. 726-739
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    Sheqin Dong, Jianchang Ao, Fuqi Luo:
    Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure. 740-752
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    Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi:
    Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods. 753-765
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    Jai-Ming Lin, Che-Chun Lin:
    Placement Density Aware Power Switch Planning Methodology for Power Gating Designs. 766-777
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    Hsi-An Chien, Ye-Hong Chen, Szu-Yuan Han, Hsiu-Yu Lai, Ting-Chi Wang:
    On Refining Row-Based Detailed Placement for Triple Patterning Lithography. 778-793
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    Ahmet Gokcen Mahmutoglu, Alper Demir:
    Modeling and Simulation of Low-Frequency Noise in Nano Devices: Stochastically Correct and Carefully Crafted Numerical Techniques. 794-807
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    Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, Ramesh Karri:
    Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. 808-821
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    Sachhidh Kannan, Naghmeh Karimi, Ramesh Karri, Ozgur Sinanoglu:
    Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories. 822-834
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    Cristiana Bolchini, Luca Cassano, Paolo Garza, Elisa Quintarelli, Fabio Salice:
    An Expert CAD Flow for Incremental Functional Diagnosis of Complex Electronic Boards. 835-848
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    Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan:
    Repairing a 3-D Die-Stack Using Available Programmable Logic. 849-861
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    Hyunchan Park, Hanchan Jo, Cheol-Ho Hong, Young-Pil Kim, See-hwan Yoo, Chuck Yoo:
    SSD-Tailor: Automated Customization System for Solid-State Drives. 862-866
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    Ignacio Garcia-Vargas, Raouf Senhadji-Navarro:
    Finite State Machines With Input Multiplexing: A Performance Study. 867-871

Volume 34, Number 6, June 2015

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    Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia:
    Guest Editorial Special Section on Hardware Security and Trust. 873-874
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    Nektarios Georgios Tsoutsos, Michail Maniatakos:
    The HEROIC Framework: Encrypted Computation Without Shared Keys. 875-888
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    Jeroen Delvaux, Dawu Gu, Dries Schellekens, Ingrid Verbauwhede:
    Helper Data Algorithms for PUF-Based Key Generation: Overview and Analysis. 889-902
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    Xiaolin Xu, Amir Rahmati, Daniel E. Holcomb, Kevin Fu, Wayne P. Burleson:
    Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells. 903-914
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    Suvadeep Hajra, Debdeep Mukhopadhyay:
    Reaching the Limit of Nonprofiling DPA. 915-927
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    Franck Courbon, Jacques J. A. Fournier, Philippe Loubet-Moundi, Assia Tria:
    Combining Image Processing and Laser Fault Injections for Characterizing a Hardware AES. 928-936
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    Rafal Baranowski, Michael A. Kochte, Hans-Joachim Wunderlich:
    Fine-Grained Access Management in Reconfigurable Scan Networks. 937-946
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    Ke Huang, Yu Liu, Nenad Korolija, John M. Carulli, Yiorgos Makris:
    Recycled IC Detection Based on Statistical Methods. 947-960
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    Stephen M. Plaza, Igor L. Markov:
    Solving the Third-Shift Problem in IC Piracy With Test-Aware Logic Locking. 961-971
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    Chao Chen, José L. Abellán, Ajay Joshi:
    Managing Laser Power in Silicon-Photonic NoC Through Cache and NoC Reconfiguration. 972-985
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    Xueqian Zhao, Zhonghai Lu:
    Heuristics-Aided Tightness Evaluation of Analytical Bounds in Networks-on-Chip. 986-999
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    Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
    ILP-Based Alleviation of Dense Meander Segments With Prioritized Shifting and Progressive Fixing in PCB Routing. 1000-1013
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    Fangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu:
    Information-Theoretic Syndrome Evaluation, Statistical Root-Cause Analysis, and Correlation-Based Feature Selection for Guiding Board-Level Fault Diagnosis. 1014-1026
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    Biruk W. Mammo, Valeria Bertacco, Andrew DeOrio, Ilya Wagner:
    Post-Silicon Validation of Multiprocessor Memory Consistency. 1027-1037
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    Jaeyong Chung, Jibum Kim:
    Segment Delay Learning From Quantized Path Delay Measurements. 1038-1042

Volume 34, Number 7, July 2015

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    Fanshu Jiao, Sergio Montano, Cristian Ferent, Alex Doboli, Simona Doboli:
    Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies. 1045-1058
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    Haotian Liu, Luca Daniel, Ngai Wong:
    Model Reduction and Simulation of Nonlinear Circuits via Tensor Decomposition. 1059-1069
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    Jaeha Kung, Duckhwan Kim, Saibal Mukhopadhyay:
    On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing. 1070-1081
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    Gage Hills, Jie Zhang, Max Marcel Shulaker, Hai Wei, Chi-Shuen Lee, Arjun Balasingam, H.-S. Philip Wong, Subhasish Mitra:
    Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations. 1082-1095
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    Shupeng Sun, Xin Li, Hongzhou Liu, Kangsheng Luo, Ben Gu:
    Fast Statistical Analysis of Rare Circuit Failure Events via Scaled-Sigma Sampling for High-Dimensional Variation Space. 1096-1109
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    Woojoo Lee, Yanzhi Wang, Massoud Pedram:
    Optimizing a Reconfigurable Power Distribution Network in a Multicore Platform. 1110-1123
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    Irith Pomeranz:
    A Multicycle Test Set Based on a Two-Cycle Test Set With Constant Primary Input Vectors. 1124-1132
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    Mao-Hsu Yen, Hung-Kuan Yen, Chu Yu:
    Comment on "On Optimal Hyperuniversal and Rearrangeable Switch Box Designs". 1133-1137
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    Amit Chhabra, Harsh Rawat, Mohit Jain, Pascal Tessier, Daniel Pierredon, Laurent Bergher, Promod Kumar:
    FALPEM: Framework for Architectural-Level Power Estimation and Optimization for Large Memory Sub-Systems. 1138-1142
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    Yuan Cao, Le Zhang, Chip-Hong Chang, Shoushun Chen:
    A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications. 1143-1147
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    Jie Zhang, Feng Yuan, Lingxiao Wei, Yannan Liu, Qiang Xu:
    VeriTrust: Verification for Hardware Trust. 1148-1161
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    Mafalda Cortez, Said Hamdioui, Ali Kaichouhi, Vincent van der Leest, Roel Maes, Geert Jan Schrijen:
    Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems. 1162-1175
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    Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy:
    Optimizating Emerging Nonvolatile Memories for Dual-Mode Applications: Data Storage and Key Generator. 1176-1187
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    Begül Bilgin, Benedikt Gierlichs, Svetla Nikova, Ventzislav Nikov, Vincent Rijmen:
    Trade-Offs for Threshold Implementations Illustrated on AES. 1188-1200
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    Weiwei Shan, Xingyuan Fu, Zhipeng Xu:
    A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA. 1201-1205

Volume 34, Number 8, August 2015

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    Debashis Banerjee, Shyam Kumar Devarakond, Xian Wang, Shreyas Sen, Abhijit Chatterjee:
    Real-Time Use-Aware Adaptive RF Transceiver Systems for Energy Efficiency Under BER Constraints. 1209-1222
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    Zidong Du, Avinash Lingamneni, Yunji Chen, Krishna V. Palem, Olivier Temam, Chengyong Wu:
    Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators. 1223-1235
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    Pawel Swierczynski, Marc Fyrbiak, Philipp Koppe, Christof Paar:
    FPGA Trojans Through Detecting and Weakening of Cryptographic Primitives. 1236-1249
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    Yu-Min Lee, Chi-Wen Pan, Pei-Yu Huang, Chi-Ping Yang:
    LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs. 1250-1263
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    Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, Shaojun Wei:
    An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy, and Performance in Reconfigurable NoC Architectures. 1264-1277
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    Wing Chiu Jason Tam, Ronald Shawn Blanton:
    LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering. 1278-1290
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    Sourabh Khandelwal, Harshit Agarwal, Juan Pablo Duarte, Kaiman Chan, Sagnik Dey, Yogesh Singh Chauhan, Chenming Hu:
    Modeling STI Edge Parasitic Current for Accurate Circuit Simulations. 1291-1294
• 
  • 
  • 
  • 
  • 
    Georg T. Becker:
    On the Pitfalls of Using Arbiter-PUFs as Building Blocks. 1295-1307
• 
  • 
  • 
  • 
  • 
    Andreas Gornik, Amir Moradi, Jürgen Oehm, Christof Paar:
    A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation. 1308-1319
• 
  • 
  • 
  • 
  • 
    Giovanni Agosta, Alessandro Barenghi, Gerardo Pelosi, Michele Scandale:
    The MEET Approach: Securing Cryptographic Embedded Software Against Side Channel Attacks. 1320-1333
• 
  • 
  • 
  • 
  • 
    Durga Prasad Sahoo, Phuong Ha Nguyen, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty:
    A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks. 1334-1343
• 
  • 
  • 
  • 
  • 
    Miltos D. Grammatikakis, Kyprianos Papadimitriou, Polydoros Petrakis, Antonis Papagrigoriou, George Kornaros, Ioannis Christoforakis, Othon Tomoutzoglou, George Tsamis, Marcello Coppola:
    Security in MPSoCs: A NoC Firewall and an Evaluation Framework. 1344-1357
• 
  • 
  • 
  • 
  • 
    Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker:
    Formal Vulnerability Analysis of Security Components. 1358-1369

Volume 34, Number 9, September 2015

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  • 
  • 
  • 
    Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen, Tung-Chieh Chen, Chin-Chieh Lee, Jou-Chun Lin:
    A Fast Prototyping Framework for Analog Layout Migration With Planar Preservation. 1373-1386
• 
  • 
  • 
  • 
  • 
    Yun Liang, Tulika Mitra, Lei Ju:
    Instruction Cache Locking Using Temporal Reuse Profile. 1387-1400
• 
  • 
  • 
  • 
  • 
    Xuan Wang, Jiang Xu, Zhe Wang, Kevin J. Chen, Xiaowen Wu, Zhehui Wang, Peng Yang, Luan H. K. Duong:
    An Analytical Study of Power Delivery Systems for Many-Core Processors Using On-Chip and Off-Chip Voltage Regulators. 1401-1414
• 
  • 
  • 
  • 
  • 
    Santiago Pagani, Jian-Jia Chen, Jörg Henkel:
    Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme. 1415-1428
• 
  • 
  • 
  • 
  • 
    Chia-Hung Liu, Ting-Wei Chiang, Juinn-Dar Huang:
    Reactant Minimization in Sample Preparation on Digital Microfluidic Biochips. 1429-1440
• 
  • 
  • 
  • 
  • 
    Zoha Pajouhi, Swagath Venkataramani, Karthik Yogendra, Anand Raghunathan, Kaushik Roy:
    Exploring Spin-Transfer-Torque Devices for Logic Applications. 1441-1454
• 
  • 
  • 
  • 
  • 
    Jaeil Lim, Hyunyul Lim, Sungho Kang:
    3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability. 1455-1466
• 
  • 
  • 
  • 
  • 
    Honghuang Lin, Peng Li:
    Circuit Performance Classification With Active Learning Guided Sampling for Support Vector Machines. 1467-1480
• 
  • 
  • 
  • 
  • 
    Xiao Li, Fan Yang, Dake Wu, Zhenya Zhou, Xuan Zeng:
    MOS Table Models for Fast and Accurate Simulation of Analog and Mixed-Signal Circuits Using Efficient Oscillation-Diminishing Interpolations. 1481-1494
• 
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  • 
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  • 
    Suleyman Tosun, Vahid Babaei Ajabshir, Ozge Mercanoglu, Özcan Özturk:
    Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips. 1495-1508
• 
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  • 
  • 
  • 
    Sandeep Chatterjee, Mohammad Fawaz, Farid N. Najm:
    Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties. 1509-1522
• 
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  • 
    Mukesh Agrawal, Krishnendu Chakrabarty:
    Test-Cost Modeling and Optimal Test-Flow Selection of 3-D-Stacked ICs. 1523-1536

Volume 34, Number 10, October 2015

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  • 
    Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha:
    TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. 1537-1557
• 
  • 
  • 
  • 
  • 
    Hassan Eldib, Chao Wang, Mostafa M. I. Taha, Patrick Schaumont:
    Quantitative Masking Strength: Quantifying the Power Side-Channel Resistance of Software Code. 1558-1568
• 
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  • 
  • 
  • 
    Reza Azarderakhsh, Mehran Mozaffari Kermani:
    High-Performance Two-Dimensional Finite Field Multiplication and Exponentiation for Cryptographic Applications. 1569-1576
• 
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  • 
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    Chongxi Bao, Domenic Forte, Ankur Srivastava:
    Temperature Tracking: Toward Robust Run-Time Detection of Hardware Trojans. 1577-1585
• 
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    Mojtaba Ebrahimi, Adrian Evans, Mehdi Baradaran Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi:
    Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor. 1586-1599
• 
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  • 
  • 
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    Zhu Wang, Zonghua Gu, Min Yao, Zili Shao:
    Endurance-Aware Allocation of Data Variables on NVM-Based Scratchpad Memory in Real-Time Embedded Systems. 1600-1612
• 
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    Anatoly Prihozhy, Endri Bezati, Ab Al-Hadi Ab Rahman, Marco Mattavelli:
    Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs. 1613-1626
• 
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    Lorenzo Zuolo, Cristian Zambelli, Rino Micheloni, Marco Indaco, Stefano Di Carlo, Paolo Prinetto, Davide Bertozzi, Piero Olivo:
    SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives. 1627-1638
• 
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    Xueqian Zhao, Lengfei Han, Zhuo Feng:
    A Performance-Guided Graph Sparsification Approach to Scalable and Robust SPICE-Accurate Integrated Circuit Simulations. 1639-1651
• 
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  • 
  • 
  • 
    Chris C. N. Chu, Wai-Kei Mak:
    Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography. 1652-1663
• 
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  • 
  • 
    Guangshuo Liu, Jinpyo Park, Diana Marculescu:
    Procrustes1: Power Constrained Performance Improvement Using Extended Maximize-Then-Swap Algorithm. 1664-1676
• 
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  • 
    Yun Liang, Xiaolong Xie, Guangyu Sun, Deming Chen:
    An Efficient Compiler Framework for Cache Bypassing on GPUs. 1677-1690
• 
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  • 
  • 
  • 
    Carlos Fernando Teodósio Soares, Antonio Petraglia:
    Automatic Placement to Improve Capacitance Matching Using a Generalized Common-Centroid Layout and Spatial Correlation Optimization. 1691-1695
• 
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    Alexander Korobkov, Amit Agarwal, Subramanian Venkateswaran:
    Efficient FinFET Device Model Implementation for SPICE Simulation. 1696-1699

Volume 34, Number 11, November 2015

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  • 
  • 
    Samarjit Chakraborty, S. Ramesh:
    Guest Editorial Special Section on Automotive Embedded Systems and Software. 1701-1703
• 
  • 
  • 
  • 
  • 
    Xiaoqing Jin, Alexandre Donzé, Jyotirmoy V. Deshmukh, Sanjit A. Seshia:
    Mining Requirements From Closed-Loop Control Models. 1704-1717
• 
  • 
  • 
  • 
  • 
    Carles Hernández, Jaume Abella:
    Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems. 1718-1729
• 
  • 
  • 
  • 
  • 
    Chung-Wei Lin, Lei Rao, Paolo Giusto, Joseph D'Ambrosio, Alberto L. Sangiovanni-Vincentelli:
    Efficient Wire Routing and Wire Sizing for Weight Minimization of Automotive Systems. 1730-1741
• 
  • 
  • 
  • 
  • 
    Chuansheng Dong, Haibo Zeng, Minghua Chen:
    Online Algorithms for Automotive Idling Reduction With Effective Statistics. 1742-1755
• 
  • 
  • 
  • 
  • 
    Jeyavijayan Rajendran, Aman Ali, Ozgur Sinanoglu, Ramesh Karri:
    Belling the CAD: Toward Security-Centric Electronic System Design. 1756-1769
• 
  • 
  • 
  • 
  • 
    Armin Alaghi, John P. Hayes:
    STRAUSS: Spectral Transform Use in Stochastic Circuit Synthesis. 1770-1783
• 
  • 
  • 
  • 
  • 
    Bing Li, Ulf Schlichtmann:
    Statistical Timing Analysis and Criticality Computation for Circuits With Post-Silicon Clock Tuning Elements. 1784-1797
• 
  • 
  • 
  • 
  • 
    Sandeep Koranne:
    DÉJÀ VU: An Entropy Reduced Hash Function for VLSI Layout Databases. 1798-1807
• 
  • 
  • 
  • 
  • 
    Johann Knechtel, Evangeline F. Y. Young, Jens Lienig:
    Planning Massive Interconnects in 3-D Chips. 1808-1821
• 
  • 
  • 
  • 
  • 
    Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak:
    Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. 1822-1835
• 
  • 
  • 
  • 
  • 
    Shi-Yu Huang, Meng-Ting Tsai, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
    General Timing-Aware Built-In Self-Repair for Die-to-Die Interconnects. 1836-1846
• 
  • 
  • 
  • 
  • 
    Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
    Isometric Test Data Compression. 1847-1859
• 
  • 
  • 
  • 
  • 
    Mottaqiallah Taouil, Mahmoud Masadeh, Said Hamdioui, Erik Jan Marinissen:
    Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic. 1860-1872
• 
  • 
  • 
  • 
  • 
    Sergej Deutsch, Krishnendu Chakrabarty, Erik Jan Marinissen:
    Robust Optimization of Test-Access Architectures Under Realistic Scenarios. 1873-1884

Volume 34, Number 12, December 2015

• 
  • 
  • 
  • 
  • 
    Nima Jafarzadeh, Maurizio Palesi, Saeedeh Eskandari, Shaahin Hessabi, Ali Afzali-Kusha:
    Low Energy yet Reliable Data Communication Scheme for Network-on-Chip. 1892-1904
• 
  • 
  • 
  • 
  • 
    Boxun Li, Peng Gu, Yi Shan, Yu Wang, Yiran Chen, Huazhong Yang:
    RRAM-Based Analog Approximate Computing. 1905-1917
• 
  • 
  • 
  • 
  • 
    Chia-Hung Liu, Kuo-Cheng Shen, Juinn-Dar Huang:
    Reactant Minimization for Sample Preparation on Microfluidic Biochips With Various Mixing Models. 1918-1927
• 
  • 
  • 
  • 
  • 
    Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux, Philip Brisk:
    Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars. 1928-1941
• 
  • 
  • 
  • 
  • 
    Michael Wainberg, Vaughn Betz:
    Robust Optimization of Multiple Timing Constraints. 1942-1953
• 
  • 
  • 
  • 
  • 
    Mohsen Riahi Alam, Mostafa Ersali Salehi Nasab, Sied Mehdi Fakhraie:
    Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating. 1954-1963
• 
  • 
  • 
  • 
  • 
    Yarui Peng, Dusan Petranovic, Sung Kyu Lim:
    Multi-TSV and E-Field Sharing Aware Full-chip Extraction and Mitigation of TSV-to-Wire Coupling. 1964-1976
• 
  • 
  • 
  • 
  • 
    Chao Zhang, Wenjian Yu, Qing Wang, Yiyu Shi:
    Fast Random Walk Based Capacitance Extraction for the 3-D IC Structures With Cylindrical Inter-Tier-Vias. 1977-1990
• 
  • 
  • 
  • 
  • 
    Isuru Nawinne, Haris Javaid, Roshan G. Ragel, Swarnalatha Radhakrishnan, Sri Parameswaran:
    Exploring Multilevel Cache Hierarchies in Application Specific MPSoCs. 1991-2003
• 
  • 
  • 
  • 
  • 
    Irith Pomeranz:
    Computation of Seeds for LFSR-Based Diagnostic Test Generation. 2004-2012
• 
  • 
  • 
  • 
  • 
    Vasileios Tenentes, S. Saqib Khursheed, Daniele Rossi, Sheng Yang, Bashir M. Al-Hashimi:
    DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test. 2013-2024
• 
  • 
  • 
  • 
  • 
    Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
    Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. 2025-2038
• 
  • 
  • 
  • 
  • 
    Shi-Yu Huang, Meng-Ting Tsai, Hua-Xuan Li, Zeng-Fu Zeng, Kun-Han Hans Tsai, Wu-Tung Cheng:
    Nonintrusive On-Line Transition-Time Binning and Timing Failure Threat Detection for Die-to-Die Interconnects. 2039-2048
• 
  • 
  • 
  • 
  • 
    Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jörg Henkel:
    Multicast FullHD H.264 Intra Video Encoder Architecture. 2049-2053

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