ACM Transactions on Reconfigurable Technology and Systems, Volume 11 (original) (raw)

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Volume 11, Number 1, March 2018

Special Section on FCCM 2016

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    Jason D. Bakos:
    Introduction to the Special Section on FCCM'16.
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    Henry Wong, Vaughn Betz, Jonathan Rose:
    High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. 1:1-1:22
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    James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
    KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. 2:1-2:22
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    Hans Giesen, Benjamin Gojman, Raphael Rubin, Ji Kim, André DeHon:
    Continuous Online Self-Monitoring Introspection Circuitry for Timing Repair by Incremental Partial-Reconfiguration (COSMIC TRIP). 3:1-3:23

Regular Papers

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    Zhuoran Zhao, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ganghee Lee, Ediz Cetin, Oliver Diessel:
    Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems. 4:1-4:23
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    Muhammed Al Kadi, Benedikt Janßen, Jones Yudi Mori, Michael Hübner:
    General-Purpose Computing with Soft GPUs on FPGAs. 5:1-5:22
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    Kosuke Tatsumura, Sadegh Yazdanshenas, Vaughn Betz:
    Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs. 6:1-6:22
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    Rob Stewart, Kirsty Duncan, Greg Michaelson, Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace:
    RIPL: A Parallel Image Processing Language for FPGAs. 7:1-7:24
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    Farheen Fatima Khan, Andy Gean Ye:
    An Evaluation on the Accuracy of the Minimum-Width Transistor Area Models in Ranking the Layout Area of FPGA Architectures. 8:1-8:23

Volume 11, Number 2, November 2018

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    Deshya Wijesundera, Alok Prakash, Thambipillai Srikanthan, Achintha Ihalage:
    Framework for Rapid Performance Estimation of Embedded Soft Core Processors. 9:1-9:21
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    Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio C. Buttazzo, Jörg Henkel:
    Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs. 10:1-10:24
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    Oleg Petelin, Vaughn Betz:
    Wotan: Evaluating FPGA Architecture Routability without Benchmarks. 11:1-11:23
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    N. Nalla Anandakumar, M. Prem Laxman Das, Somitra Kumar Sanadhya, Mohammad S. Hashmi:
    Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve. 12:1-12:19
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    Marc-André Daigneault, Jean-Pierre David:
    Automated Synthesis of Streaming Transfer Level Hardware Designs. 13:1-13:22

Volume 11, Number 3, December 2018

Special Issue on Deep learning on FPGAs

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    Deming Chen, Andrew Putnam, Steven J. E. Wilton:
    Introduction to the Special Section on Deep Learning in FPGAs. 14:1-14:3
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    Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot:
    High-Efficiency Convolutional Ternary Neural Networks with Custom Adder Trees and Weight Compression. 15:1-15:24
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    Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers:
    FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. 16:1-16:23
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    Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu:
    Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. 17:1-17:24
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    Paolo Meloni, Alessandro Capotondi, Gianfranco Deriu, Michele Brian, Francesco Conti, Davide Rossi, Luigi Raffo, Luca Benini:
    NEURAghe: Exploiting CPU-FPGA Synergies for Efficient and Flexible CNN Inference Acceleration on Zynq SoCs. 18:1-18:24
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    Shuanglong Liu, Hongxiang Fan, Xinyu Niu, Ho-Cheung Ng, Yang Chu, Wayne Luk:
    Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. 19:1-19:22
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    Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz:
    You Cannot Improve What You Do not Measure: FPGA vs. ASIC Efficiency Gaps for Convolutional Neural Network Inference. 20:1-20:23
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    Bita Darvish Rouhani, Siam Umar Hussain, Kristin E. Lauter, Farinaz Koushanfar:
    ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in Clouds Using FPGAs. 21:1-21:21
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    Jincheng Yu, Guangjun Ge, Yiming Hu, Xuefei Ning, Jiantao Qiu, Kaiyuan Guo, Yu Wang, Huazhong Yang:
    Instruction Driven Cross-layer CNN Accelerator for Fast Detection on FPGA. 22:1-22:23

Volume 11, Number 4, January 2019

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