ACM Transactions on Reconfigurable Technology and Systems, Volume 14 (original) (raw)

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Volume 14, Number 1, November 2020

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    Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier:
    CoNFV: A Heterogeneous Platform for Scalable Network Function Virtualization. 1:1-1:29
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    Alexander E. Beasley, Christopher T. Clarke, Robert J. Watson:
    An OpenGL Compliant Hardware Implementation of a Graphic Processing Unit Using Field Programmable Gate Array-System on Chip Technology. 2:1-2:24
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    Kaan Kara, Gustavo Alonso:
    PipeArch: Generic and Context-Switch Capable Data Processing on FPGAs. 3:1-3:28
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    Soheil Mohajer, Zhiheng Wang, Kia Bazargan, Yuyang Li:
    Parallel Unary Computing Based on Function Derivatives. 4:1-4:25
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    Nikolaos Kyparissas, Apostolos Dollas:
    Large-scale Cellular Automata on FPGAs: A New Generic Architecture and a Framework. 5:1-5:32

Volume 14, Number 2, July 2021

Special Section on FPL2019

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    Adriaan Peetermans, Vladimir Rozic, Ingrid Verbauwhede:
    Design and Analysis of Configurable Ring Oscillators for True Random Number Generation Based on Coherent Sampling. 7:1-7:20
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    Shenghsun Cho, Mrunal Patel, Michael Ferdman, Peter A. Milder:
    Practical Model Checking on FPGAs. 8:1-8:18
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    Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu, Derek Chiou:
    Specializing FGPU for Persistent Deep Learning. 10:1-10:23

Regular Paper

Volume 14, Number 3, September 2021

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    Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo:
    Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. 12:1-12:21
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    Endri Taka, Konstantinos Maragos, George Lentaris, Dimitrios Soudris:
    Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs. 13:1-13:30
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    Arif Sasongko, I. M. Narendra Kumara, Arief Wicaksana, Frédéric Rousseau, Olivier Muller:
    Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams. 14:1-14:25
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    Enrico Reggiani, Emanuele Del Sozzo, Davide Conficconi, Giuseppe Natale, Carlo Moroni, Marco D. Santambrogio:
    Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components. 15:1-15:33
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    Abeer Y. Al-Hyari, Hannah Szentimrey, Ahmed Shamli, Timothy Martin, Gary Gréwal, Shawki Areibi:
    A Deep Learning Framework to Predict Routability for FPGA Circuit Placement. 16:1-16:28

Volume 14, Number 4, December 2021

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    Yi-Hsiang Lai, Ecenur Ustun, Shaojie Xiang, Zhenman Fang, Hongbo Rong, Zhiru Zhang:
    Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. 17:1-17:39
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    Tao Yang, Zhezhi He, Tengchuan Kou, Qingzheng Li, Qi Han, Haibao Yu, Fangxin Liu, Yun Liang, Li Jiang:
    BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization. 18:1-18:28
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    Mark Wijtvliet, Henk Corporaal, Akash Kumar:
    CGRA-EAM - Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures. 19:1-19:28
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    Zhenghua Gu, Wenqin Wan, Jundong Xie, Chang Wu:
    Dependency Graph-based High-level Synthesis for Maximum Instruction Parallelism. 20:1-20:15
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    José Romero Hung, Chao Li, Pengyu Wang, Chuanming Shao, Jinyang Guo, Jing Wang, Guoyong Shi:
    ACE-GCN: A Fast Data-driven FPGA Accelerator for GCN Embedding. 21:1-21:23
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    Sebastian Sabogal, Alan D. George, Gary Crum:
    Reconfigurable Framework for Resilient Semantic Segmentation for Space Applications. 22:1-22:32

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