ACM Transactions on Reconfigurable Technology and Systems, Volume 6 (original) (raw)

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Volume 6, Number 1, May 2013

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    Tarek Ould-Bachir, Jean-Pierre David:
    Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators. 1:1-1:21
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    Yan Zhang, Fan Zhang, Zheming Jin, Jason D. Bakos:
    An FPGA-Based Accelerator for Frequent Itemset Mining. 2:1-2:17
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    Roel Meeuws, Sayyed Arash Ostadzadeh, Carlo Galuzzi, Vlad Mihai Sima, Razvan Nane, Koen Bertels:
    Quipu: A Statistical Model for Predicting Hardware Resources. 3:1-3:25
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    Florent de Dinechin, Pedro Echeverría, Marisa López-Vallejo, Bogdan Pasca:
    Floating-Point Exponentiation Units for Reconfigurable Computing. 4:1-4:15
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    Christopher E. Neely, Gordon J. Brebner, Weijia Shang:
    ReShape: Towards a High-Level Approach to Design and Operation of Modular Reconfigurable Systems. 5:1-5:23

Volume 6, Number 2, July 2013

Special Section on 19th Reconfigurable Architectures Workshop (RAW 2012)

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    Diana Goehringer, René Cumplido:
    Introduction to the special section on 19th reconfigurable architectures workshop (RAW 2012). 6:1
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  Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker:
  JITPR: A framework for supporting fast application's implementation onto FPGAs. 7:1-7:12
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  Jan Heisswolf, Aurang Zaib, Andreas Weichslgartner, Ralf König, Thomas Wild, Jürgen Teich, Andreas Herkersdorf, Jürgen Becker:
  Virtual networks - distributed communication resource management. 8:1-8:14
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  Thilan Ganegedara, Viktor K. Prasanna:
  A comprehensive performance analysis of virtual routers on FPGA. 9:1-9:21
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    Joydip Das, Steven J. E. Wilton:
    Towards development of an analytical model relating FPGA architecture parameters to routability. 10:1-10:24
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    Chun-Hsian Huang, Pao-Ann Hsiung:
    Virtualizable hardware/software design infrastructure for dynamically partially reconfigurable systems. 11:1-11:18

Volume 6, Number 3, October 2013

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    Hanyu Liu, Senthilkumar Thoravi Rajavel, Ali Akoglu:
    Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms. 12:1-12:21
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    Gayatri Mehta, Carson Crawford, Xiaozhong Luo, Natalie Parde, Krunalkumar Patel, Brandon Rodgers, Anil Kumar Sistla, Anil Yadav, Marc Reisner:
    UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies. 13:1-13:26
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    Javier Hormigo, Gabriel Caffarena, Juan P. Oliver, Eduardo I. Boemo:
    Self-Reconfigurable Constant Multiplier for FPGA. 14:1-14:17
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    Farnaz Gharibian, Lesley Shannon, Peter Jamieson, Kevin Chung:
    Analyzing System-Level Information's Correlation to FPGA Placement. 15:1-15:21

Volume 6, Number 4, December 2013

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    Franjo Plavec, Zvonko G. Vranesic, Stephen Brown:
    Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. 16:1-16:37
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    T. Ananthan, M. V. Vaidyan:
    A Reconfigurable Parallel Hardware Implementation of the Self-Tuning Regulator. 17:1-17:21
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    Yoon Kah Leow, Ali Akoglu, Susan Lysecky:
    An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures. 18:1-18:22
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    Yosi Ben-Asher, Ron Meldiner, Nadav Rotem:
    Optimizing Wait States in the Synthesis of Memory References with Unpredictable Latencies. 19:1-19:9

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