ACM Transactions on Reconfigurable Technology and Systems, Volume 9 (original) (raw)

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Volume 9, Number 1, November 2015

Special Section on the 2014 International Symposium on Applied Reconfigurable Computing

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    Joonseok Park, Pedro C. Diniz:
    Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware. 1:1-1:13
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    Neil Scicluna, Christos-Savvas Bouganis:
    ARC 2014: A Multidimensional FPGA-Based Parallel DBSCAN Architecture. 2:1-2:15
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    Pascal Sasdrich, Tim Güneysu:
    Implementing Curve25519 for Side-Channel-Protected Elliptic Curve Cryptography. 3:1-3:15
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    Jianfeng Zhang, Paul Chow, Hengzhu Liu:
    An Enhanced Adaptive Recoding Rotation CORDIC. 4:1-4:25

Special Section on the 2014 International Symposium on Applied Reconfigurable Computing

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    Diana Goehringer, Marco D. Santambrogio, João M. P. Cardoso, Koen Bertels:
    Guest Editorial ARC 2014. 5:1-5:2
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    Karel Heyse, Jente Basteleus, Brahim Al Farisi, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell:
    On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure. 6:1-6:18
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    Rui Policarpo Duarte, Christos-Savvas Bouganis:
    ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation. 7:1-7:17
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    Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado:
    ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree. 8:1-8:16

Volume 9, Number 2, February 2016

Special Section on RAW2014

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    Jianfeng Zhang, Paul Chow, Hengzhu Liu:
    CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition. 9:1-9:22
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    Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides:
    Separation Logic for High-Level Synthesis. 10:1-10:23
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    Hirak J. Kashyap, Ricardo Chaves:
    Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs. 11:1-11:22
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    Jinwei Xu, Jingfei Jiang, Yong Dou, Xiaolong Shen, Zhiqiang Liu:
    Coarse-Grained Architecture for Fingerprint Matching. 12:1-12:15

Special Section on RAW2014

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    Marco D. Santambrogio, Ramachandran Vaidyanathan:
    Guest Editorial RAW 2014. 13:1-13:2
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    Ali Mustafa Zaidi, David J. Greaves:
    Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. 14:1-14:22
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    Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck:
    RAW 2014: Random Number Generators on FPGAs. 15:1-15:21
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    Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno:
    A Reconfigurable Architecture for the Detection of Strongly Connected Components. 16:1-16:19

Volume 9, Number 3, July 2016

Special Issue on Reconfigurable Components with Source Code

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    Nachiket Kapre:
    Optimizing Soft Vector Processing in FPGA-Based Embedded Systems. 17:1-17:17
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    André DeHon, Derek Chiou:
    Introduction to Special Issue on Reconfigurable Components with Source Code. 19:1-19:2
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    Xin Fang, Miriam Leeser:
    Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs. 20:1-20:17
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    David Wilson, Greg Stitt:
    The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator. 21:1-21:23
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    Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
    Modular Switched Multiported SRAM-Based Memories. 22:1-22:26
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    Greg Stitt, Eric Schwartz, Patrick Cooke:
    A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs. 23:1-23:22

Volume 9, Number 4, September 2016

Regular Papers

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    Zain-ul-Abdin, Bertil Svensson:
    A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing. 24:1-24:22
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    Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber:
    FPGA-Based Dynamically Reconfigurable SQL Query Processing. 25:1-25:24
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    Eric Matthews, Lesley Shannon, Alexandra Fedorova:
    Shared Memory Multicore MicroBlaze System with SMP Linux Support. 26:1-26:22
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    Ting Yu, Chris P. Bradley, Oliver Sinnen:
    ODoST: Automatic Hardware Acceleration for Biomedical Model Integration. 27:1-27:24

Special Section on Field Programmable Gate Arrays (FPGA) 2015

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    Deming Chen:
    Introduction. 28:1-28:2
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    Evan Wegley, Yanhua Yi, Qinhai Zhang:
    Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs. 29:1-29:22
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    Edin Kadric, David Lakata, André DeHon:
    Impact of Parallelism and Memory Architecture on FPGA Communication Energy. 30:1-30:23
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    Alex Rodionov, David Biancolin, Jonathan Rose:
    Fine-Grained Interconnect Synthesis. 31:1-31:22

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