dblp: A. Chen (disambiguation) (original) (raw)

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• > Home > Persons

This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.

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2020 – today

• 2025
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  [c8]
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    Geoffrey W. Burr, H. Tsai, Irem Boybat, William Andrew Simon, Julian Büchel, Athanasios Vasilopoulos, Pritish Narayanan, Andrea Fasoli, Kohji Hosokawa, Manuel Le Gallo, M. Ishii, Yasuteru Kohda, Atsuya Okazaki, A. Chen, Charles Mackin, Elena Ferro, Kaoutar El Maghraoui, Hadjer Benmeziane, T. Philicelli, Corey Lammie, Alexander M. Friz, Jose Luquin, S. Jain, Abu Sebastian, V. Narayanan:
    Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited). CICC 2025: 1-6
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  [c7]
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    H. Tsai, Hadjer Benmeziane, Irem Boybat, Julian Büchel, Pritish Narayanan, Manuel Le Gallo, S. Jain, Athanasios Vasilopoulos, W. Simon, Kohji Hosokawa, M. Ishii, Yasuteru Kohda, A. Chen, Charles Mackin, Kaoutar El Maghraoui, Atsuya Okazaki, Alexander M. Friz, Jose Luquin, Abu Sebastian, V. Narayanan, Geoffrey W. Burr:
    Analog AI Accelerators for Transformer-based Language Models: Hardware, Workload, and Power Performance. IMW 2025: 1-4
• 2024
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  [c6]
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    R. Mathur, R. Sisodia, A. Chen, A. Singh, S. Thyagarajan, A. Cubeta, C. Andrieux, A. Sowden, Y. K. Chong:
    A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology. VLSI Technology and Circuits 2024: 1-2
• 2022
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  [c5]
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    R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong:
    5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. CICC 2022: 1-2
• 2021
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  [c4]
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    Liu Yu, Kailiang Chen, Yue Chang, A. Chen, Qidi Yin, Hangwei Zhang:
    A New Correlation Model of IoT Attack Based on Attack Tree. DASC/PiCom/CBDCom/CyberSciTech 2021: 930-935
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  [c3]
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    Jing Tao, A. Chen, Kai Liu, Kailiang Chen, Fengyuan Li, Peng Fu:
    Recommendation Method of Honeynet Trapping Component Based on LSTM. DASC/PiCom/CBDCom/CyberSciTech 2021: 952-957

2010 – 2019

• 2018
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  [c2]
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    Sri Navaneeth Easwaran, A. Chen, T. Duryea, D. Rollman:
    40V High Side PSI5 Transceiver with 65dBµV Conducted Emission Level in a BiCMOS Process. BCICTS 2018: 279-282

2000 – 2009

• 2006
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  [c1]
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    John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
    A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC 2006: 2564-2571

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