CIRCT: exported verilog from mlir can't be synthesized with yosys (original) (raw)

November 26, 2025, 2:33am 1

Given the input firrtl file, I can produce synthesizable Verilog with firtool --lowering-options=disallowLocalVariables,disallowPackedArrays foo.fir.

However, when I try to first emit mlir with firrtool --ir-hw and the same lowering option, then generate Verilog from it with

circt-opt \
    --lower-seq-to-sv \
    --lower-hw-to-sv \
    --hw-memory-sim \
    --prettify-verilog \
    --export-verilog

Yosys now reports ERROR: syntax error, unexpected OP_CAST. Here is the Verilog snippet that triggers this error:

  wire [31:0][2:0] _GEN =
    '{3'h1,
      3'h1,
      3'h1,
      3'h1,
      3'h1,
      3'h1,
      3'h1,
      3'h1,
      3'h1,
      ...

It seems that packed array is still being generated. Is there a way to enforce disallowPackedArrays during mlir to Verilog translation? Any other approach to get away with this, mainly the cast op, is also OK. Thanks in advance! :slight_smile:

uenoku November 26, 2025, 3:10am 2

Could you try inserting -hw-legalize-modules before prettify-verilog?

zihan0822 November 26, 2025, 3:54am 3

Yeah, it works now with this additional flag. Thank you @uenoku!

You can also try to use firtool again to process the MLIR file. For example:

firtool foo.fir --ir-hw -o foo.mlir
firtool foo.mlir -o foo.sv

If you give firtool an MLIR file, it will skip the FIR file parsing and process the MLIR directly. That way, you get the exact same Verilog pass pipeline as if you called firtool without the --ir-hw option :smiley: