FIRRTL equivalent to Yosys's $initstate (original) (raw)

September 25, 2024, 9:29am 1

I’m building a embedded HDL library in Rust that generates FIRRTL, but I’m running into a problem when I’m trying to run formal verification using SymbiYosys on the output: I can’t figure out how to drive the reset input to 1 for the first cycle and 0 for the rest. Currently, the circuit never gets reset so none of the registers come up in valid states. If I were writing verilog or rtlil (yosys’s IR), I would just use $initstate, or verilog’s initial, but I can’t find the FIRRTL equivalent. Is there some intrinsic I’m missing? or will I have to generate a separate verilog module that I can write $initstate in and then use it as an external module?

uenoku September 25, 2024, 12:50pm 2

Unfortunately the short answer is no. Currently we cannot specify the register initial value in FIRRTL level (we can do that in lower-level dialects, seq or sv today). Actually I’ve been working on ground work towards initial values for FIRRTL register but it’s not finished yet. Implementing it as an external module looks reasonable workaround to me.