HGLDD wrong var_name reference? (original) (raw)

March 28, 2024, 12:16pm 1

Hello, I was updating my demo project after my PR has been approved (Make firtool options for `elaborateGeneratedModule` in `workspace` pa… · chipsalliance/chisel@9177535 · GitHub).
However, when I emit the HGLDD with debug information “-g” it returns a different result compared to what I obtained before.

I tried to emit the HGLDD for this circuit (the example I used in the meeting last Wednesday):

class Bar extends Module {
  val io = IO(new Bundle {
    val a   = Input(Bool())
    val b   = Input(Bool())
    val out = Output(Bool())
  })

  val inputSum  = IO(Input(new MyBundleT(8)))
  val outputSum = IO(Output(SInt(8.W)))
  when(inputSum.nestedBundle.z === true.B) {
    outputSum := inputSum.a.asSInt + inputSum.b.asSInt
  }.otherwise {
    outputSum := inputSum.a.asSInt - inputSum.b.asSInt
  }

  val wire = Wire(Bool())
  wire   := io.a & io.b
  io.out := wire
}

And in the final hgldd now it outputs wire_0 which is the verilog name and not the firrtl node name. I checked the emitted firrtl file and it also has wire as name.

{
  "var_name": "wire_0", // it should be wire
  "hgl_loc": {
    "begin_column": 18,
    "begin_line": 35,
    "end_column": 18,
    "end_line": 35,
    "file": 1
  },
  "value": {"sig_name":"wire_0"},
  "type_name": "logic"
}

uenoku March 28, 2024, 12:38pm 2

I think that’s intentional behaviour unfortunately because wire is verilog reserved keyword. Currently hgldd var names are legalized into valid verilog names in the emission due tools limitation as noted here: circt/lib/Target/DebugInfo/EmitHGLDD.cpp at 37fbe5e5f5c7a07064d02cea8bf4e8454178fc0e · llvm/circt · GitHub

I agree we should emit correct variable names eventually

CC: @fabianschuiki

rameloni March 28, 2024, 12:43pm 3

I do agree with this, but I guess sig_name should contain the verilog name while var_name the source firrtl name.

You’re right @rameloni, var_name is the Chisel/FIRRTL name and sig_name is whatever the emitted Verilog ended up being. However, as @uenoku mentioned, HGLDD requires names to not be reserved Verilog keywords – a limitation which we could lift if we add another format to CIRCT, for example one that your waveform viewer could ingest. That’s why you see wire_0 as var_name as well; it’s just a uniquified/legalized version of the FIRRTL name wire. If you call it something else, like val cable = ... you’ll see a "var_name": "cable" in the output.