Topics tagged arm (original) (raw)

Instrumenting code after register allocation for ARM backends

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33

April 18, 2025

Senior Developer for Compilers and Static Analysis @ Samsung Research Poland

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138

February 12, 2025

Adding function calls in Machine IR after Register Allocation

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65

January 31, 2025

Clang-tidy tries to analyze an STM32 assembly file located in compile_commands.json

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97

August 29, 2024

Clang + lld apparently can't find cross compile libraries

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307

June 10, 2024

Custom libc++ for C++20 coroutines on bare metal embedded Arm

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193

June 10, 2024

Setting -mcpu=cortex-a9 -mfpu=neon for ARM target does not make clang pick memcpy optimized for the co-processor

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260

June 6, 2024

Cross-compilation from x86_64 to armv7 using Clang

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178

April 8, 2024

Does clang support to generate GOT-based position indenpendent code with pic-register?

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1753

March 24, 2024

[RFC]: Strengthen Relaxed Atomics Implementation behind `-mstrict-rlx-atomics` Flag

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1630

December 22, 2023

Stack space allocation problem under different optimization levels of ARM

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129

December 14, 2023

Bring features of fromelf of ARM to llvm-objcopy

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686

November 28, 2023

SME in MLIR status (20/10/2023)

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585

October 20, 2023

How to substitute `SP` register with `R7` in Cortex-M code generation?

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329

October 6, 2023

[RFC] Creating a ArmSME Dialect

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3419

June 9, 2023

How can I use the GCC sysroot for ARM when using Clang?

2

1038

April 5, 2023

Why passing a structure by value is compiled into passing by reference without byval attribute?

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1223

November 28, 2022

Cross compilation of libcxx for baremetal ARMv7m with hard floating point support

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1898

November 9, 2022

Why does march=native not work on Apple M1?

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5959

September 27, 2022

RFC: Removal of armv2/2A/3/3M target options

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624

September 8, 2022

[AArch64] How to combine a sequence IR cross BasicBlock?

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431

September 7, 2022

Adding debug info to a raw binary

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484

July 11, 2022

Clang SME ACLE intrinsics

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839

June 27, 2022

[AArch64] Is the cost of MSUB instruction is significantly higher than that of the MADD instruction?

5

347

June 11, 2022

Is it time to start upstreaming the CHERI support to LLVM?

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1519

May 9, 2022

Does the update of sp redundant in spill/reload code?

2

263

May 4, 2022

[AArch64] Does we need support value bigger than 2 for alloc_align

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254

April 7, 2022

Switching to GCC C runtime linkage for the baremetal driver

6

1501

March 30, 2022

[AArch64] which vesion is should be expected in pass simple-register-coalescing?

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392

March 25, 2022

Program stopped without a specific reason. How to interpret this?

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648

March 18, 2022