Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADC (original) (raw)

Abstract

This paper presents a precision wide range Delta Sigma ADC SC1601 (SC1601 is the product number of ADC) with programmable gain amplifier (PGA) and programmable output data rate features. The ADC offers four fully differential input channels. Each channel can be programmed with a gain of 1 to 128 in binary steps i.e. in powers of 2. The ADC uses a second order delta sigma modulator (DSM) followed by a digital sinc\(^3\) filter. The output data rate of the ADC is also programmable from 312.5 Hz to 2.5 kHz either to achieve higher accuracy or higher speed. The ADC also offers on chip offset and gain calibration features to reduce the offset and gain errors. The serial interface of ADC is SPI\(^{TM}\) compatible. The SC1601 ADC is fabricated in 0.18 \(\upmu \)m CMOS process at Semi-Conductor Laboratory (SCL). The total power consumption of the ADC is 4 mW and it consumes total silicon area of 2.25 mm\(^2\). SC1601 ADC achieves a maximum ENOB of 19.15 bits at a data rate of 312.5 Hz with a full scale range of 1.22 V. The ADC requires a supply voltage of 3.3 V and 1.8 V and can operate in a wide temperature range of −55\(^{\circ }\)C to 125\(^{\circ }\)C. SC1601 ADC is developed for the satellite launch vehicle telemetry system.

Supported by Semi-Conductor Laboratory.

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References

  1. de la Rosa, J.M., Schreier, R., Pun, K., Pavan, S.: Next-generation delta-sigma converters: trends and perspectives. IEEE J. Emerg. Sel. Top. Circuits Syst. 5(4), 484–499 (2015). https://doi.org/10.1109/JETCAS.2015.2502164
    Article Google Scholar
  2. Norsworthy, S.R., Schreier, R., Temes, G.C.: Delta-Sigma Data Converters: Theory, Design and Simulation, NewYork, NY. Wiley, USA (1997)
    Google Scholar
  3. del Río, R., Mederio, F., Pérez-Verdú, B., de la Rosa, J.M., Rodríguez-Vázquez, Á.: CMOS Cascade Sigma-Delta Modulators for Sensors and Telecom. Springer, Netherlands (2006). https://doi.org/10.1007/1-4020-4776-2
    Book Google Scholar
  4. Sreelal S. P., et al.: A versatile, software programmable telemetry system for satellite launch vehicles. In: Proceedings of 2006 International Telemetering Conference (ITC 06), San Diego, USA, pp. 06–18-04 (2006)
    Google Scholar
  5. ADS1218: 8-Channel, 24-Bit Analog-to-Digital Converter Data sheet, Texas Instruments Inc., USA (2005)
    Google Scholar
  6. Enz, C.C., Temes, G.C.: Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization. Proc. IEEE 84(11), 1584–1614 (1996)
    Article Google Scholar
  7. Samadpoor Rikan, B., et al.: A sigma-delta ADC for signal conditioning IC of automotive piezo-resistive pressure sensors with over 80 dB SNR. Sensors 18, 4199 (2018). https://doi.org/10.3390/s18124199
  8. Benvenuti, L., Catania, A., Manfredini, G., Ria, A., Piotto, M., Bruschi, P.: Design strategies and architectures for ultra-low-voltage delta-sigma ADCs. Electronics 10, 1156 (2021). https://doi.org/10.3390/electronics10101156
    Article Google Scholar
  9. Nagaraj, K., Vlach, J., Viswanathan, T.R., Singhal, K.: Switched-capacitor integrator with reduced sensitivity to amplifier gain. Electron. Lett. 22(21), 1103–1105 (1986)
    Article Google Scholar
  10. Saeed, M.A., Gadhia, J., Jatana, H.S.: Accurate analysis of settling error in CDS integrator based sigma delta modulators. Annu. IEEE India Conf. (INDICON) 2015, 1–6 (2015). https://doi.org/10.1109/INDICON.2015.7443484
    Article Google Scholar
  11. Yao, L., Steyaert, M.S.J., Sansen, W.: A 1-V 140-/spl mu/W 88-dB audio sigma-delta modulator in 90-nm CMOS. IEEE J. Solid-State Circ. 39(11), 1809–1818 (2004). https://doi.org/10.1109/JSSC.2004.835825
  12. Yin, G.M., Eynde, F.O., Sansen, W.: A high-speed CMOS comparator with 8-b resolution. IEEE J. Solid-State Circ. 27(2), 208–211 (1992)
    Google Scholar
  13. Hogenauer, E.: An economical class of digital filters for decimation and interpolation. IEEE Trans. Acoust. Speech Signal Process. 29(2), 155–162 (1981). https://doi.org/10.1109/TASSP.1981.1163535
    Article Google Scholar
  14. Park, S.: Multi-stage decimation filter design technique for high-resolution sigma-delta A/D converters. IEEE Trans. Instrum. Meas. 41(6), 868–873 (1992). https://doi.org/10.1109/19.199424
    Article Google Scholar
  15. Baker, B.: A glossary of analog-to-digital specifications and performance characteristics. Texas Instruments Application Report, SBAA147B (2011)
    Google Scholar

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Acknowledgements

The authors are very grateful to S. N. Mittal of VLSI Test and Application Development Division (VTAD), Semi-Conductor Laboratory for carrying out rigorous testing of SC1601 ADC. In addition, the authors would like to thank Dr. Devarshi Mrinal Das of Electrical Engg. Dept., IIT Ropar for his fruitful discussions during the drafting of this paper.

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Authors and Affiliations

  1. Semi-Conductor Laboratory, S.A.S. Nagar, Mohali, 160071, Punjab, India
    Mohd Asim Saeed, Deep Sehgal & Surinder Singh
  2. Electrical Engg. Department, IIT Ropar, Rupnagar, 140071, Punjab, India
    Mohd Asim Saeed

Authors

  1. Mohd Asim Saeed
  2. Deep Sehgal
  3. Surinder Singh

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Correspondence toMohd Asim Saeed .

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Editors and Affiliations

  1. Department of Electrical Engineering, Indian Institute of Technology Jammu, Jammu, India
    Ambika Prasad Shah
  2. Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, Roorkee, India
    Sudeb Dasgupta
  3. Department of Electronics Engineering, Sardar Vallabhbhai National Institute of Technology Surat, Surat, India
    Anand Darji
  4. Department of Computer Science and Engineering, Indian Institute of Technology Tirupati, Tirupati, India
    Jaynarayan Tudu

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Saeed, M.A., Sehgal, D., Singh, S. (2022). Four Differential Channels, Programmable Gain, Programmable Data Rate Delta Sigma ADC. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8\_16

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