A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering (original) (raw)

Abstract

A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the test set adopts a series of preprocessed strategies including don’t care bit based 2-D adjusting, Hamming Distance based 2-D reordering and test cube matrix based two transpose, all steps will be orderly executed in interspersed way. The six largest ISCAS’89 benchmark circuits verify the proposed method. Experimental results show that the switching activities are effectively reduced when the test set is loaded for on-chip scan testing. ASDFR with MT-filling scheme ensures high compression ratio, the scan-in test power dissipation is further decreased by don’t care bit based 2-D adjusting and Hamming Distance 2-D reordering. In addition, the BIST TPG method with less test application time and smaller algorithm complexity can be widely applied to actual chip design without adding extra decoder area overhead.

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References

  1. Ahmed N, Tehranipour MH, Nourani M (2004) Low power pattern generation for BIST archite cture. Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS '04, vol. 2, pp 689–692
  2. Basker P, Arulmurugan A (2012) Survey of low power testing of VLSI circuits. Int Conf Comput Commun Inform (ICCCI) 1(7):10
    Google Scholar
  3. Chandra A, Chakrabarty K (2000) Test data compression for system-on-a-chip using Golomb codes. VLSI Test Symposium, 2000. Proceedings 18th IEEE, vol. 113, no. 120
  4. Chandra A, Chakrabarty K (2002) Low-power scan testing and test data compression for system-on-a-chip. IEEE Trans Comput Aided Des Integr Circ Syst 21(5):597–604
    Article Google Scholar
  5. Chandra A, Chakrabarty K (2003) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Trans Comput 52(8):1076,1088
    Article Google Scholar
  6. ChandraA, Chakrabarty K (2002) Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. Design Automation Conference, 2002. Proceedings 39th, pp 673–678
  7. El-Maleh AH (2008) Test data compression for system-on-a-chip using extended frequency-directed run-length code. IET Comput Digit Tech 2(3):155–163
    Article Google Scholar
  8. Hellebrand S, Würtenberger A (2002) Alternating run-length coding–A technique for improved test data compression. In: Handouts 3rd IEEE International Workshop on Test Resource Partitioning, Baltimore
  9. Jas A, Ghosh-Dastidar J, Mom-Eng N, Touba NA (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Trans Comput Aided Des Integr Circ Syst 22(6):797–806
    Article Google Scholar
  10. Mehla US, Dasgupta KS, Devashrayee NM (2010) Hamming distance based reordering and column wise bit stuffing with difference vector: a better scheme for test data compression with run length based codes. 23rd International Conference on VLSI Design. VLSID '10, vol. 33, no. 38, p 3
  11. Mehta US, Devashrayee NM, Dasgupta KS (2010) Hamming distance based 2-D reordering with power efficient don't care bit filling: optimizing the test data compression method. Int Symp Syst Chip (SoC) 1(7):29–30
    Google Scholar
  12. Nourani M, Tehranipoor M, Ahmed N (2008) Low-transition test pattern generation for BIST-based applications. IEEE Trans Comput 57(3):303–315
    Article MathSciNet Google Scholar
  13. Sankaralingam K, Oruganti RR, Touba NA (2000) Static compaction techniques to control scan vector power dissipation. In: 18th IEEE VLSI Test Symposium, vol. 35, no. 40
  14. Seongmoon W, Gupta SK (2002) DS-LFSR: a BIST TPG for low switching activity. IEEE Trans Comput Aided Des Integr Circ Syst 21(7):842–851
    Article Google Scholar
  15. Sivanantham S, Mallick PS, Raja Paul Perinbam J (2014) Low-power selective pattern compression for scan-based test applications. Comput Electr Eng 40(4):1053–1063
    Article Google Scholar
  16. Yuan H, Mei J, Song H, Guo K (2014) Test data compression for system-on-a-chip using count compatible pattern run-length coding. J Electron Test Theory Appl 30(2):237–242
    Article Google Scholar

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Acknowledgements

This research work was supported by the National Natural Science Foundation of China (61001049, 61372149 and 61370189). Scholarship sponsored by China Scholarship Council [2013] 3018.

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Authors and Affiliations

  1. College of Electronic Information and Control Engineering, Beijing University of Technology, Beijing, 100124, China
    Haiying Yuan, Kun Guo, Jiaping Mei & Hongying Song
  2. Department of Electronic Engineering, Tsinghua University, Beijing, 100084, China
    Xun Sun

Authors

  1. Haiying Yuan
  2. Kun Guo
  3. Xun Sun
  4. Jiaping Mei
  5. Hongying Song

Corresponding author

Correspondence toHaiying Yuan.

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Responsible Editor: C. A. Papachristou

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Yuan, H., Guo, K., Sun, X. et al. A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering.J Electron Test 31, 43–52 (2015). https://doi.org/10.1007/s10836-015-5507-7

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