Low Power AES Using 8-Bit and 32-Bit Datapath Optimization for Small Internet-of-Things (IoT) (original) (raw)

References

  1. Roman, R., Najera, P., & Lopez, J. (2011). Securing the internet of things. Computer, 44(9), 51–58.
    Article Google Scholar
  2. Barki, A., Bouabdallah, A., Gharout, S., & Traore, J. (2016). M2M security: Challenges and solutions. IEEE Commun. Surveys Tuts., 18(2), 1241–1254.
    Article Google Scholar
  3. Keoh, S. L., Kumar, S., & Tschofenig, H. (2014). Securing the internet of things: A standardization perspective. IEEE Internet Things, 1(3), 265–275.
    Article Google Scholar
  4. Yu, W., & Kose, S. (2017). A lightweight masked AES implementation for securing IoT against CPA attacks. IEEE Transactions on Circuits and Systems I: Regular Papers, 64(11), 2934–2944.
    Article MathSciNet Google Scholar
  5. Tsai, K., Huang, Y., Leu, F., You, I., Huang, Y., & Tsai, C. (2018). AES-128 based secure low power communication for LoRaWAN IoT environments. IEEE Access, 6, 45325–45334.
    Article Google Scholar
  6. Niu, Y., Zhang, J., Wang, A., & Chen, C. (2019). An efficient collision power attack on AES encryption in edge computing. IEEE Access, 7, 18734–18748.
    Article Google Scholar
  7. Bui, D., Puschini, D., Bacles-Min, S., Beigne, E., & Tran, X. (2017). AES Datapath optimization strategies for low-power low-energy multisecurity-level internet-of-things applications. IEEE VLSI Syst., 25(12), 3281–3290.
    Article Google Scholar
  8. Agwa, S., Yahya, E., & Ismail, Y. (2017). Power efficient AES core for IoT constrained devices implemented in 130nm CMOS. In Proc. 2017 IEEE ISCAS, Baltimore, pp. 1–4.
  9. National Institute of Standard Technology (NIST) (2001). Federal Information Processing Standards (FIPS) publication 197. Advanced Encryption Standard.
  10. Wang, Y., & Ha, Y. (2013). FPGA-based 40.9-Gbits/s masked AES with area optimization for storage area network. IEEE Transactions on Circuits and Systems II: Express Briefs, 60(1), 36–40.
    Article Google Scholar
  11. Wong, M. M., Wong, M. L. D., Nandi, A. K., & Hijazin, I. (2012). Construction of optimum composite Fied architecture for compact high-throughput AES S-boxes. IEEE VLSI Syst., 20(6), 1151–1155.
    Article Google Scholar
  12. El-meligy, N., Anin, M., Yahya, E., & Ismail, Y. (2017). 130nm low power asynchronous AES Core. In Proc. 2017 IEEE ISCAS, Baltimore, pp. 1–4.
  13. Good, T., & Benaissa, M. (2010). 692-nW advanced encryption standard (AES) on a 0.13-μm CMOS. IEEE VLSI Syst., 18(12), 1753–1757.
    Article Google Scholar
  14. Hocquet, C., Kamel, D., Regazzoi, F., Legat, J., Flandre, D., Bol, D., & Standaert, F. (2011). Harvesting the potential of nano-CMOS for lightweight cryptography an ultra-low-voltage 65 nm AES coprocessor for passive RFID tags. JCEN, 1(1), 79–86.
    Google Scholar
  15. Shastry, P., Agnihotri, A., Kachhwaha, D., Singh, J., & Sutaone, M. (2011). A combinational logic implementation of S-box of AES. In Proc. 2011 IEEE 54th International MWSCAS, Seoul, pp. 1–4.
  16. Zhao, W., Ha, Y., & Alioto, M. (2015). AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption. In Proc. 2015 IEEE ISCAS, Lisbon, pp. 2349–2352.
  17. Mathew, S., Satpathy, S., Suresh, V., Anders, M., Kaul, H., Agarwal, A., Hsu, S., Chen, G., & Krishnamurthy, R. (2015). 340 mV-1.1 V, 289 Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22 nm tri-gate CMOS. IEEE Journal of Solid-State Circuits, 50(4), 1048–1058.
    Article Google Scholar

Download references