$\mu$ m$^{2}$ and a 0.080 $\mu$ m$^{2}$ 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve ${\rm V}_{{\rm MIN}}$ of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the ${\rm V}_{{\rm MIN}}$ of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 ${\rm V}_{{\rm MIN}}$ with 200 mV improvement by NBL, and 0.47 ${\rm V}_{{\rm MIN}}$ for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved ${\rm V}_{{\rm MIN}}$ reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.">

A 14 nm FinFET 128 Mb SRAM With V $_{\rm MIN}$ Enhancement Techniques for Low-Power Applications (original) (raw)

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