$LC$ resonator and to suppress the 3rd harmonic by introducing a transformer inter-winding capacitor feedback path. A fractional-N all-digital phase locked loop (ADPLL) with a transformer-based digitally controlled oscillator (DCO) is employed to reduce power consumption as well as improve modulation quality. The transmitter was fabricated in 40-nm CMOS technology, occupying an active area of 0.48mm2. Experimental results show a 26% drain efficiency with −10dBm PA output and 4dB tunable range. A 2mW total power consumption was measured with a TX efficiency of 5% and an energy efficiency of 2nJ/bit. The measured 2nd and 3rd harmonic distortion of the output were −44.3dBm and −57.2dBm, respectively, with on-chip matching network. The measured FSK error of CPM was 2.3% with an M of 2 and 1.57% with an M of 4.">

A 2 nJ/bit, 2.3% FSK Error Fully Integrated Sub-2.4 GHz Transmitter With Duty-Cycle Controlled PA for Medical Band (original) (raw)

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