Determining appropriate precisions for signals in fixed-point IIR filters | Proceedings of the 40th annual Design Automation Conference (original) (raw)

Published: 02 June 2003 Publication History

Abstract

This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This analysis is necessary because FPGAs, unlike fixed register size digital signal processors, allow custom bit widths. Within the framework, the designer determines the number of bits necessary for representing the constant coefficients and the internal signals in the filter. The coefficient bit widths are determined by accounting for the sensitivity of the filter's pole and zero locations with respect to the coefficient perturbations. The internal signal bit widths are determined by calculating theoretical bounds on the ranges of the signals, and on the errors introduced by truncation in the fixed-point hardware. The bounds tell how many bits are required at any point in the computation in order to avoid overflow and guarantee a prescribed degree of accuracy in the filter output. The bounds form the basis for a methodology for the fixed-point digital filter implementation. The methodology is applied to the implementation of a second-order filter used as a compensator in a magnetic bearing control system.

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Altera Corporation, "APEX DSP Development Board (Starter Version)," Data Sheet, April 2002.

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P.H. Bauer, "Absolute response error bounds for floating point digital filters in state space representation," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 42, No. 9, September 1995, pp. 610--613.

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G.A. Constantinides, P.Y.K. Cheung, and W. Luk, "The Multiple Wordlength Paradigm," IEEE Symposium for Custom Computing Machines, 2001.

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J. C. Doyle, B. A. Francis, and A. R. Tannenbaum, Feedback Control Theory, Macmillan, New York, 1992.

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B.D. Green and L.E. Turner, "New limit cycle bounds for digital filters," IEEE Transactions on Circuits and Systems, Vol. 35, No. 4, April 1988, pp. 365--374.

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F. W. Krach, B. P. Frackelton, J. E. Carletta, and R. J. Veillette, "FPGA-based implementation of digital control for a magnetic bearing," to appear in the 2003 American Control Conference.

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cover image ACM Conferences

DAC '03: Proceedings of the 40th annual Design Automation Conference

June 2003

1014 pages

Copyright © 2003 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 June 2003

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Author Tags

  1. design methodology
  2. field programmable gate array
  3. finite word length effects
  4. infinite impulse response filter

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DAC '03 Paper Acceptance Rate 152 of 628 submissions, 24%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Joan Carletta

The University of Akron, Akron, OH

Robert Veillette

The University of Akron, Akron, OH

Frederick Krach

The University of Akron, Akron, OH

Zhengwei Fang

The University of Akron, Akron, OH