Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline (original) (raw)

Abstract

AutoDock Vina (Vina) is a widely adopted molecular docking tool, often regarded as a standard or used as a baseline in numerous studies. However, its computational process is highly time-consuming. The pioneering field-programmable gate array (FPGA)-based accelerator of Vina, known as Vina-FPGA, offers a high energy-efficiency approach to speed up the docking process. However, the computation modules in the Vina-FPGA design are not efficiently used. This is due to Vina exhibiting irregular behaviors in the form of nested loops with changing upper bounds and differing control flows. Fortunately, Vina employs the Monte Carlo iterative search method, which requires independent computations for different random initial inputs. This characteristic provides an opportunity to implement further parallel computation designs. To this end, this paper proposes Vina-FPGA2, an inter-module pipeline design for further accelerating Vina-FPGA. First, we use individual computational task (Task) independence by sequentially filling Tasks into computation modules. Then, we implement an inter-module pipeline parallel design by the Tag Checker module and architectural modifications, named Vina-FPGA2-Baseline. Next, to achieve resource-efficient hardware implementation, we describe it as an optimization problem and develop a reinforcement learning-based solver. Targeting the Xilinx UltraScale XCKU060 platform, this solver yields a more efficient implementation, named Vina-FPGA2-Enhanced. Finally, experiments show that Vina-FPGA2-Enhanced achieves an average 12.6× performance improvement over the central processing unit (CPU) and a 3.3× improvement over Vina-FPGA. Compared to Vina-GPU, Vina-FPGA2 achieves a 7.2× enhancement in energy efficiency.

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Data availability

The data that support the findings of this study are available from the corresponding authors upon reasonable request.

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Authors and Affiliations

1. School of Integrated Circuits, Southeast University, Nanjing, 210096, China
   Ming Ling, Shidi Tang & Xin Li
2. Department of Electronics and Informatics, Vrije Universiteit Brussel, Brussels, 1050, Belgium
   Ruiqi Chen
3. VeriMake Innovation Laboratory, Nanjing Renmian Integrated Circuit Company Ltd., Nanjing, 210088, China
   Yanxiang Zhu

Authors

1. Ming Ling
2. Shidi Tang
3. Ruiqi Chen
4. Xin Li
5. Yanxiang Zhu

Contributions

Xin LI and Ruiqi CHEN drafted the paper. Ming LING, Shidi TANG, Ruiqi CHEN, and Yanxiang ZHU revised the paper. Ruiqi CHEN and Shidi TANG finalized the paper.

Corresponding authors

Correspondence toMing Ling or Ruiqi Chen.

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All the authors declare that they have no conflict of interest.

Additional information

Project supported by the National Natural Science Foundation of China (No. 92464301) and the Big Data Computing Center of Southeast University

List of supplementary materials

1 The algorithm introduction for AutoDock-Vina

2 Reinforcement learning based design space exploration

Algorithm S1 Iterated local search global optimizer

Algorithm S2 BFGS Quasi–Newton algorithm in Vina

Algorithm S3 AG linear search algorithm

Algorithm S4 Finding optimal configuration parameters of _N_A, n t,a

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Ling, M., Tang, S., Chen, R. et al. Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline.Front Inform Technol Electron Eng 26, 2215–2230 (2025). https://doi.org/10.1631/FITEE.2400941

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• Received: 22 October 2024
• Accepted: 28 September 2025
• Published: 03 December 2025
• Version of record: 03 December 2025
• Issue date: November 2025
• DOI: https://doi.org/10.1631/FITEE.2400941

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