ISCA Archive - Parallel partitioning techniques for the DTW algorithm in speech recognition (original) (raw)

Parallel partitioning techniques for the DTW algorithm in speech recognition

G. Stainhaouer, George Carayannis

Two parallel techniques far the partitioned parallel implementation of a DTW algorithm are discussed in this paper. The parallel architectures proposed, are independent of the number of processors available, if they da not exceed a specific number related to the DTW strategy. The first technique leads to a circular array, while the second to a linear array of processing elements (PE). The advantage of both architectures is that their efficiency remains almost unchanged when the number of PEs varies.