Etienne Hirt | Swiss Federal Institute of Technology (ETH) (original) (raw)

Papers by Etienne Hirt

IEEE Aerospace and Electronic Systems Magazine, 2005

Un aspect de la presente invention concerne un dispositif qui determine de maniere non invasive l... more Un aspect de la presente invention concerne un dispositif qui determine de maniere non invasive la concentration d'une substance dans une cible. Ce dispositif comprend une premiere electrode, un circuit de mesure et un systeme de traitement des donnees. Dans un mode de realisation de ce dispositif, la premiere electrode peut etre electriquement isolee de la cible, par exemple au moyen d'une couche de revetement en materiau isolant qui recouvre la premiere electrode.

2018 7th Electronic System-Integration Technology Conference (ESTC), 2018

Space applications demand highly reliable and low weight systems. Three-dimensional moulded inter... more Space applications demand highly reliable and low weight systems. Three-dimensional moulded interconnect device (3D-MID) processes have the potential to fulfil the requirements by combining the (electronic) packaging with routing and mechanical structure. In this paper 3D-MID technology is reviewed, most promising techniques identified and test vehicles are investigated with the focus on space usage within the ESA Artes 5.1 program.

Today’s design of computer systems is mainly limited by the achievable I/O bandwidth. Chip design... more Today’s design of computer systems is mainly limited by the achievable I/O bandwidth. Chip designers try to avoid this barrier by designing larger and larger chips. Package designers on the other hand are facing ICs with smaller and smaller pad pitches for more and more I/Os. This traditional separation between chip and package design blocks new solutions. But a close co-operation of chip and package designers allows new partitioning options by combining area I/O with new chip design. The co-operation brings up more and faster I/Os which are easy to connect. The achievable improvements are exemplified on a generic microprocessor system design. 1 Motivation State of the art processors show ever increasing internal clock rates to improve performance. But the external clock rate as well the I/O bus width hardly match this trend as shown in the roadmap (table 1). It was tried to overcome this discrepancy of off-chip bandwidth to on-chip speed by adding several levels of caches, which en...

To date designers seek to achieve ever smaller systems with ever more functionality, but more and... more To date designers seek to achieve ever smaller systems with ever more functionality, but more and more they face the interconnection technology as a show stopper. To overcome this bottleneck we propose a chip-package codesign approach; a close cooperation between chip and package designers exploiting the synergism. Our approach distributes the on-chip pads all over the IC area near the pads associated core area. This technique results into smaller ICs with more and faster I/Os being much easier to package. In this paper, a case study for a Pentium class system shows why other approaches such as wire bond, re-routing and chip size package (CSP) have shortcomings. Finally, we present an outlook to new system architectures that are enabled by area I/O: A processor system with first level cache on separate ICs instead of being integrated on the CPU itself.

Two Pentium Multi-Chip Modules (MCM) containing a Pentium Processor, part of the Intel Chipset an... more Two Pentium Multi-Chip Modules (MCM) containing a Pentium Processor, part of the Intel Chipset and 512kBytes 2 level cache are compared in this paper. Since these two modules are targeted at different markets, they are implemented in quite different technologies. Both modules were developed at the Electronics Laboratory of the ETH Zürich. One module is built on a four layer MCM-D substrate and packaged in a Plastic Stud Grid Array Package (PSGA), developed by IMEC. The complete module is treated like a standard SMT component. The second module is a mix of SMT and Chip-on-Board (COB) technology. Therefore the substrate is an eight layer laminate with laserdrilled microvias, which is populated on both sides. The second level interconnection is provided by two SMT connectors on two sides of the module. The comparison of these two MCMs should reveal the impact of a chosen target market on partitioning and technology.

Medical device technology, 2003

Standard HDP technologies such as COB can be involved early in the development stage. They help t... more Standard HDP technologies such as COB can be involved early in the development stage. They help to form the development process and to meet size requirements without exhausting the development budget. Higher HDP production costs are negligible compared with the total development, field test and regulatory approval costs. Using HDP for miniaturisation, it is possible to make applications of previously lab-scale equipment for WMDs and for implants.

Space applications demand highly reliable, low weight systems. 3-dimensional moulded interconnect... more Space applications demand highly reliable, low weight systems. 3-dimensional moulded interconnect device (3D-MID) processes have the potential to fulfil the requirements by combining the (electronic) packaging with routing and mechanical structures. In this paper 3D-MID technology is reviewed, most promising techniques identified and test vehicles investigated with the focus on their future use in space. This work is performed within the ESA Artes 5.1 programme.

In this paper, we present and discuss the evaluation of end user acceptance of a wrist device, de... more In this paper, we present and discuss the evaluation of end user acceptance of a wrist device, designed to monitor vital signs and to detect adverse situations, such as falls, unconsciousness etc. and, if necessary, to alert emergency services to the wearers need. The goals of all concerned must be taken into account if the technological advances are to be of benefit to those for whom they are being designed. After the technical assessment was made, a further study of the end users views was aimed to show the acceptance levels of elderly end users to the idea of personal monitoring, its perceived usefulness in their every day lives, and their judgment of the design. This was made in the form of a questionnaire divided into five main areas: usefulness, attractiveness, usability, comfort and acceptance, and each end user was interviewed regarding their goals. Each of the interviewees regarded their own continuing independence as a primary goal; however their views as to the possibility of achieving this goal by the use of advanced technology differed. This work was completed as part of the EMERGE project, aimed at the support of elderly people in everyday life using innovative monitoring and assistance systems, with the use of ambient and unobtrusive sensors in order to increase their safety, thereby promoting a longer period of independence, a step made necessary by the demographic increase in the elderly population in Europe.

Proceedings of Spie the International Society For Optical Engineering, 1999

Résumé/Abstract The ultra-miniature GPS receiver by μ-blox in high-density laminate technology cu... more Résumé/Abstract The ultra-miniature GPS receiver by μ-blox in high-density laminate technology currently uses wire bond interconnect for its digital part. This paper explores the cost saving potential when switching to chip-scale packages (CSP) before starting an ...

Spie Proceedings Series, 2002

Résumé/Abstract Today's quality of life is supported by medical capabilities that have not b... more Résumé/Abstract Today's quality of life is supported by medical capabilities that have not been available years ago. But these capabilities are not limited to disease treatment only; indeed there has been a paradigm shift to disease prevention and monitoring. Especially ...