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Research paper thumbnail of IEEE 802.3 100Gbps Ethernet PCS IP Design Challenges and Solutions

—Physical Coding Sublayer(PCS) is a key part of the Ethernet Physical Layer. This paper presents ... more —Physical Coding Sublayer(PCS) is a key part of the Ethernet Physical Layer. This paper presents our solutions to design challenges of the 100 Gigabit per second (Gbps) Ethernet PCS Semiconductor Intellectual Property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics implementation challenges and verification challenges. The provided solutions are based on our implementation of 100Gbps PCS IP which has being verified in both software and hardware.

Research paper thumbnail of IEEE 802.3 100Gbps Ethernet PCS IP Design Challenges and Solutions

—Physical Coding Sublayer(PCS) is a key part of the Ethernet Physical Layer. This paper presents ... more —Physical Coding Sublayer(PCS) is a key part of the Ethernet Physical Layer. This paper presents our solutions to design challenges of the 100 Gigabit per second (Gbps) Ethernet PCS Semiconductor Intellectual Property (IP) compliant with IEEE 802.3 standard. Challenges are discussed under the two topics implementation challenges and verification challenges. The provided solutions are based on our implementation of 100Gbps PCS IP which has being verified in both software and hardware.

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