VaishnaviMudaliar - Overview (original) (raw)

🛰️ Vaishnavi Mudaliar

Junior Research Fellow @ MeitY C2S | Hardware-Aware AI & FPGA Systems Researcher

Hardware-Aware AI • Deep Learning Architect • VLSI Design Specialist

🔍 Research Focus

FPGA-accelerated Machine Learning for Genomics
Hardware-Software Co-design for Edge AI
Efficient Architectures for Sequence Alignment & Basecalling

🔬 About My Research

I am a Junior Research Fellow under the Ministry of Electronics and Information Technology (MeitY) C2S initiative. My research is centered on the intersection of Machine Learning and Genomics, specifically focusing on the indigenous development of high-performance, energy-efficient hardware for life sciences.

Project Title: Implementation of ML Based DNA Sequencing Hardware Accelerator using FPGA.
The Problem: Modern DNA sequencing generates massive datasets that overwhelm traditional CPUs. My work involves designing custom silicon architectures to accelerate base-calling and alignment using ML.
Methodology: I utilize Hardware-Software Co-design to optimize Deep Learning models (such as RNNs or Transformers) for real-time genomic data processing on Edge-FPGA platforms.
Goal: To deliver a high-throughput, low-power solution that contributes to the "Atmanirbhar Bharat" mission in the semiconductor and biotech domains.

🛠️ Technical Toolkit

Area	Tools & Technologies
Hardware Description	Verilog, SystemVerilog, VHDL, HLS (C/C++)
FPGA Platforms	Xilinx Zynq-7000, UltraScale+, PYNQ Framework
EDA Tools	Xilinx Vivado, Vitis, ModelSim, Quartus
AI Frameworks	PyTorch, TensorFlow, ONNX, Model Quantization/Pruning
Languages	Python (C++ for HLS), TCL (Scripting), MATLAB

📚 Publications

I maintain a live record of my peer-reviewed research and conference proceedings on ORCID.

📝 Latest Publications

📄 5+ Publications | IEEE • Springer • Elsevier

"Hardware Acceleration of K-Means Clustering Algorithm," Lecture Notes in Networks and Systems, 2026. Read Paper
"A novel accelerated sparse Support Vector Machine (AS-SVM) algorithm for binary classification of DNA sequences," Franklin Open, 2025. Read Paper
"Optimization of Sigmoid Activation Function on FPGA: An Analysis of Linear Interpolation with Fixed-Point Representations," 2025 IEEE Recent Advances in Intelligent Computational Systems (RAICS), 2025. Read Paper
"Implementation of Banded Smith-Waterman Sequence Alignment Algorithm on CPU and FPGA," Research Square, 2024. Read Paper
"Improved ECG Lead Detection and Classification using YOLOv8," 2024 8th International Conference on Computing Communication Control and Automation Iccubea 2024, 2024. Read Paper

🌟 Featured Work

Optimization of Sigmoid Activation Function on FPGA
📍 IEEE RAICS 2025
🔗 https://doi.org/10.1109/raics66191.2025.11332583

A novel accelerated sparse Support Vector Machine (AS-SVM) algorithm for binary classification of DNA sequences
📍 Franklin Open 2025
🔗 https://doi.org/10.1016/j.fraope.2025.100427

VaishnaviMudaliar - Overview (original) (raw)