@@ -13,12 +13,8 @@ |
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#if SOC_I2S_HW_VERSION_2 |
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#undef I2S_STD_CLK_DEFAULT_CONFIG |
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-#define I2S_STD_CLK_DEFAULT_CONFIG(rate) { \ |
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- .sample_rate_hz = rate, \ |
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- .clk_src = I2S_CLK_SRC_DEFAULT, \ |
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- .ext_clk_freq_hz = 0, \ |
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- .mclk_multiple = I2S_MCLK_MULTIPLE_256, \ |
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-} |
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+#define I2S_STD_CLK_DEFAULT_CONFIG(rate) \ |
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+ { .sample_rate_hz = rate, .clk_src = I2S_CLK_SRC_DEFAULT, .ext_clk_freq_hz = 0, .mclk_multiple = I2S_MCLK_MULTIPLE_256, } |
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#endif |
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#define I2S_READ_CHUNK_SIZE 1920 |