[AArch64][SME] Fix accessing the emergency spill slot with hazard pad… · llvm/llvm-project@2481e59 (original) (raw)

`@@ -2911,12 +2911,13 @@ define i32 @vastate(i32 %x) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "targ

`

2911

2911

`; CHECK64-NEXT: mov x9, sp

`

2912

2912

`; CHECK64-NEXT: mov w20, w0

`

2913

2913

`; CHECK64-NEXT: msub x9, x8, x8, x9

`

``

2914

`+

; CHECK64-NEXT: mov x19, sp

`

2914

2915

`; CHECK64-NEXT: mov sp, x9

`

2915

``

`-

; CHECK64-NEXT: stur x9, [x29, #-208]

`

2916

``

`-

; CHECK64-NEXT: sub x9, x29, #208

`

2917

``

`-

; CHECK64-NEXT: sturh wzr, [x29, #-198]

`

2918

``

`-

; CHECK64-NEXT: stur wzr, [x29, #-196]

`

2919

``

`-

; CHECK64-NEXT: sturh w8, [x29, #-200]

`

``

2916

`+

; CHECK64-NEXT: str x9, [x19]

`

``

2917

`+

; CHECK64-NEXT: add x9, x19, #0

`

``

2918

`+

; CHECK64-NEXT: strh wzr, [x19, #10]

`

``

2919

`+

; CHECK64-NEXT: str wzr, [x19, #12]

`

``

2920

`+

; CHECK64-NEXT: strh w8, [x19, #8]

`

2920

2921

`; CHECK64-NEXT: msr TPIDR2_EL0, x9

`

2921

2922

`; CHECK64-NEXT: .cfi_offset vg, -32

`

2922

2923

`; CHECK64-NEXT: smstop sm

`

`@@ -2925,7 +2926,7 @@ define i32 @vastate(i32 %x) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "targ

`

2925

2926

`; CHECK64-NEXT: .cfi_restore vg

`

2926

2927

`; CHECK64-NEXT: smstart za

`

2927

2928

`; CHECK64-NEXT: mrs x8, TPIDR2_EL0

`

2928

``

`-

; CHECK64-NEXT: sub x0, x29, #208

`

``

2929

`+

; CHECK64-NEXT: add x0, x19, #0

`

2929

2930

`; CHECK64-NEXT: cbnz x8, .LBB33_2

`

2930

2931

`; CHECK64-NEXT: // %bb.1: // %entry

`

2931

2932

`; CHECK64-NEXT: bl __arm_tpidr2_restore

`

`@@ -2991,16 +2992,13 @@ define i32 @vastate(i32 %x) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "targ

`

2991

2992

`; CHECK1024-NEXT: mov x9, sp

`

2992

2993

`; CHECK1024-NEXT: mov w20, w0

`

2993

2994

`; CHECK1024-NEXT: msub x9, x8, x8, x9

`

``

2995

`+

; CHECK1024-NEXT: mov x19, sp

`

2994

2996

`; CHECK1024-NEXT: mov sp, x9

`

2995

``

`-

; CHECK1024-NEXT: sub x10, x29, #1872

`

2996

``

`-

; CHECK1024-NEXT: stur x9, [x10, #-256]

`

2997

``

`-

; CHECK1024-NEXT: sub x9, x29, #1862

`

2998

``

`-

; CHECK1024-NEXT: sub x10, x29, #1860

`

2999

``

`-

; CHECK1024-NEXT: sturh wzr, [x9, #-256]

`

3000

``

`-

; CHECK1024-NEXT: sub x9, x29, #2128

`

3001

``

`-

; CHECK1024-NEXT: stur wzr, [x10, #-256]

`

3002

``

`-

; CHECK1024-NEXT: sub x10, x29, #1864

`

3003

``

`-

; CHECK1024-NEXT: sturh w8, [x10, #-256]

`

``

2997

`+

; CHECK1024-NEXT: str x9, [x19]

`

``

2998

`+

; CHECK1024-NEXT: add x9, x19, #0

`

``

2999

`+

; CHECK1024-NEXT: strh wzr, [x19, #10]

`

``

3000

`+

; CHECK1024-NEXT: str wzr, [x19, #12]

`

``

3001

`+

; CHECK1024-NEXT: strh w8, [x19, #8]

`

3004

3002

`; CHECK1024-NEXT: msr TPIDR2_EL0, x9

`

3005

3003

`; CHECK1024-NEXT: .cfi_offset vg, -32

`

3006

3004

`; CHECK1024-NEXT: smstop sm

`

`@@ -3009,7 +3007,7 @@ define i32 @vastate(i32 %x) "aarch64_inout_za" "aarch64_pstate_sm_enabled" "targ

`

3009

3007

`; CHECK1024-NEXT: .cfi_restore vg

`

3010

3008

`; CHECK1024-NEXT: smstart za

`

3011

3009

`; CHECK1024-NEXT: mrs x8, TPIDR2_EL0

`

3012

``

`-

; CHECK1024-NEXT: sub x0, x29, #2128

`

``

3010

`+

; CHECK1024-NEXT: add x0, x19, #0

`

3013

3011

`; CHECK1024-NEXT: cbnz x8, .LBB33_2

`

3014

3012

`; CHECK1024-NEXT: // %bb.1: // %entry

`

3015

3013

`; CHECK1024-NEXT: bl __arm_tpidr2_restore

`