[lldb][RISCV] Support optionally disabled FPR for riscv64 (#104547) · llvm/llvm-project@660e34f (original) (raw)

`@@ -18,42 +18,15 @@

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`#define GPR_OFFSET(idx) ((idx)*8 + 0)

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`#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoPOSIX_riscv64::GPR))

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#define REG_CONTEXT_SIZE \

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(sizeof(RegisterInfoPOSIX_riscv64::GPR) + \

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sizeof(RegisterInfoPOSIX_riscv64::FPR))

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-

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`#define DECLARE_REGISTER_INFOS_RISCV64_STRUCT

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`#include "RegisterInfos_riscv64.h"

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`#undef DECLARE_REGISTER_INFOS_RISCV64_STRUCT

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const lldb_private::RegisterInfo *RegisterInfoPOSIX_riscv64::GetRegisterInfoPtr(

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const lldb_private::ArchSpec &target_arch) {

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switch (target_arch.GetMachine()) {

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case llvm::Triple::riscv64:

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return g_register_infos_riscv64_le;

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default:

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assert(false && "Unhandled target architecture.");

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return nullptr;

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}

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}

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-

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uint32_t RegisterInfoPOSIX_riscv64::GetRegisterInfoCount(

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const lldb_private::ArchSpec &target_arch) {

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switch (target_arch.GetMachine()) {

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case llvm::Triple::riscv64:

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return static_cast(sizeof(g_register_infos_riscv64_le) /

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sizeof(g_register_infos_riscv64_le[0]));

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default:

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assert(false && "Unhandled target architecture.");

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return 0;

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}

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}

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-

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`// Number of register sets provided by this context.

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`enum {

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` k_num_gpr_registers = gpr_last_riscv - gpr_first_riscv + 1,

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` k_num_fpr_registers = fpr_last_riscv - fpr_first_riscv + 1,

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k_num_register_sets = 2

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k_num_register_sets_default = 1

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`};

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`// RISC-V64 general purpose registers.

`@@ -73,38 +46,69 @@ static_assert(((sizeof g_gpr_regnums_riscv64 /

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` 1) == k_num_gpr_registers,

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` "g_gpr_regnums_riscv64 has wrong number of register infos");

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// RISC-V64 floating point registers.

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static const uint32_t g_fpr_regnums_riscv64[] = {

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fpr_f0_riscv, fpr_f1_riscv, fpr_f2_riscv, fpr_f3_riscv,

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fpr_f4_riscv, fpr_f5_riscv, fpr_f6_riscv, fpr_f7_riscv,

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fpr_f8_riscv, fpr_f9_riscv, fpr_f10_riscv, fpr_f11_riscv,

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fpr_f12_riscv, fpr_f13_riscv, fpr_f14_riscv, fpr_f15_riscv,

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fpr_f16_riscv, fpr_f17_riscv, fpr_f18_riscv, fpr_f19_riscv,

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fpr_f20_riscv, fpr_f21_riscv, fpr_f22_riscv, fpr_f23_riscv,

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fpr_f24_riscv, fpr_f25_riscv, fpr_f26_riscv, fpr_f27_riscv,

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fpr_f28_riscv, fpr_f29_riscv, fpr_f30_riscv, fpr_f31_riscv,

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fpr_fcsr_riscv, LLDB_INVALID_REGNUM};

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-

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static_assert(((sizeof g_fpr_regnums_riscv64 /

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sizeof g_fpr_regnums_riscv64[0]) -

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== k_num_fpr_registers,

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"g_fpr_regnums_riscv64 has wrong number of register infos");

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-

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`// Register sets for RISC-V64.

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static const lldb_private::RegisterSet g_reg_sets_riscv64[k_num_register_sets] =

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{{"General Purpose Registers", "gpr", k_num_gpr_registers,

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g_gpr_regnums_riscv64},

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{"Floating Point Registers", "fpr", k_num_fpr_registers,

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g_fpr_regnums_riscv64}};

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static const lldb_private::RegisterSet g_reg_set_gpr_riscv64 = {

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"General Purpose Registers", "gpr", k_num_gpr_registers,

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g_gpr_regnums_riscv64};

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static const lldb_private::RegisterSet g_reg_set_fpr_riscv64 = {

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"Floating Point Registers", "fpr", k_num_fpr_registers, nullptr};

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`RegisterInfoPOSIX_riscv64::RegisterInfoPOSIX_riscv64(

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const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags)

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const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)

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` : lldb_private::RegisterInfoAndSetInterface(target_arch),

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m_register_info_p(GetRegisterInfoPtr(target_arch)),

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m_register_info_count(GetRegisterInfoCount(target_arch)) {}

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m_opt_regsets(opt_regsets) {

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switch (target_arch.GetMachine()) {

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case llvm::Triple::riscv64: {

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// By-default considering RISC-V has only GPR.

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// Other register sets could be enabled optionally by opt_regsets.

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AddRegSetGP();

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+

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if (m_opt_regsets.AnySet(eRegsetMaskFP))

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AddRegSetFP();

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+

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break;

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}

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default:

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assert(false && "Unhandled target architecture.");

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}

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}

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+

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void RegisterInfoPOSIX_riscv64::AddRegSetGP() {

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m_register_infos.resize(k_num_gpr_registers);

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memcpy(&m_register_infos[0], g_register_infos_riscv64_gpr,

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sizeof(g_register_infos_riscv64_gpr));

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m_register_sets.push_back(g_reg_set_gpr_riscv64);

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+

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m_per_regset_regnum_range[GPRegSet] =

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std::make_pair(gpr_first_riscv, m_register_infos.size());

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}

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+

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void RegisterInfoPOSIX_riscv64::AddRegSetFP() {

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const uint32_t register_info_count = m_register_infos.size();

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const uint32_t register_set_count = m_register_sets.size();

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+

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// Filling m_register_infos.

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// For FPR case we do not need to correct register offsets and kinds

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// while for other further cases (like VPR), register offset/kind

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// should be started counting from the last one in previously added

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// regset. This is needed for the case e.g. when architecture has GPR + VPR

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// sets only.

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m_register_infos.resize(register_info_count + k_num_fpr_registers);

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memcpy(&m_register_infos[register_info_count], g_register_infos_riscv64_fpr,

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sizeof(g_register_infos_riscv64_fpr));

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+

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// Filling m_register_sets with enabled register set

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for (uint32_t i = 0; i < k_num_fpr_registers; i++)

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m_fp_regnum_collection.push_back(register_info_count + i);

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m_register_sets.push_back(g_reg_set_fpr_riscv64);

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m_register_sets.back().registers = m_fp_regnum_collection.data();

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+

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m_per_regset_regnum_range[register_set_count] =

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std::make_pair(register_info_count, m_register_infos.size());

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}

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`uint32_t RegisterInfoPOSIX_riscv64::GetRegisterCount() const {

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return m_register_info_count;

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return m_register_infos.size();

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`size_t RegisterInfoPOSIX_riscv64::GetGPRSize() const {

`@@ -117,26 +121,30 @@ size_t RegisterInfoPOSIX_riscv64::GetFPRSize() const {

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`const lldb_private::RegisterInfo *

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`RegisterInfoPOSIX_riscv64::GetRegisterInfo() const {

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return m_register_info_p;

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return m_register_infos.data();

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`size_t RegisterInfoPOSIX_riscv64::GetRegisterSetCount() const {

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return k_num_register_sets;

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return m_register_sets.size();

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`size_t RegisterInfoPOSIX_riscv64::GetRegisterSetFromRegisterIndex(

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`uint32_t reg_index) const {

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// coverity[unsigned_compare]

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if (reg_index >= gpr_first_riscv && reg_index <= gpr_last_riscv)

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return GPRegSet;

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if (reg_index >= fpr_first_riscv && reg_index <= fpr_last_riscv)

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return FPRegSet;

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for (const auto &regset_range : m_per_regset_regnum_range) {

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if (reg_index >= regset_range.second.first &&

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reg_index < regset_range.second.second)

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return regset_range.first;

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}

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`return LLDB_INVALID_REGNUM;

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bool RegisterInfoPOSIX_riscv64::IsFPReg(unsigned reg) const {

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return llvm::is_contained(m_fp_regnum_collection, reg);

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}

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+

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`const lldb_private::RegisterSet *

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`RegisterInfoPOSIX_riscv64::GetRegisterSet(size_t set_index) const {

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`if (set_index < GetRegisterSetCount())

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return &g_reg_sets_riscv64[set_index];

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return &m_register_sets[set_index];

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`return nullptr;

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